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| 74HC3GU04_15 Datasheet, PDF (6/17 Pages) NXP Semiconductors – Triple unbuffered inverter | |||
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NXP Semiconductors
74HC3GU04
Triple unbuffered inverter
tW
VI 90 %
negative
pulse
VM
10 %
0V
tf
VI
positive
pulse
tr
90 %
VM
10 %
0V
tW
VM
tr
tf
VM
VI
G
VCC
VO
DUT
RT
VCC
RL S1
CL
open
001aad983
Fig 6.
Test data is given in Table 10.
Definitions for test circuit:
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
CL = Load capacitance including jig and probe capacitance.
RL = Load resistance.
S1 = Test selection switch.
Test circuit for measuring switching times
Table 10. Test data
Type
Input
74HC3GU04
VI
GND to VCC
tr, tf
ï£ 6 ns
Load
CL
50 pF
RL
1 kï
S1 position
tPHL, tPLH
open
74HC3GU04
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 â 2 October 2013
© NXP B.V. 2013. All rights reserved.
6 of 17
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