74HC3GU04_15 Datasheet, PDF (2/17 Pages) NXP Semiconductors – Triple unbuffered inverter

NXP Semiconductors
5. Functional diagram
74HC3GU04
Triple unbuffered inverter
1 1A
3 2A
6 3A
1Y 7
2Y 5
3Y 2
Fig 1. Logic symbol
mna720
6. Pinning information
6.1 Pinning
74HC3GU04
1A 1
3Y 2
2A 3
GND 4
8 V_CC
7 1Y
6 3A
5 2Y
001aak022
Fig 3. Pin configuration SOT505-2 (TSSOP8) and
SOT765-1 (VSSOP8)
6.2 Pin description
Table 3. Pin description
Symbol
Pin
1A, 2A, 3A
1, 3, 6
1Y, 2Y, 3Y
7, 5, 2
GND
4
V_CC
8
Description
data input
data output
ground (0 V)
supply voltage
1
1
7
3
1
5
6
1
2
mna721
Fig 2. IEC logic symbol
74HC3GU04
1A 1
3Y 2
8 V_CC
7 1Y
2A 3
6 3A
GND 4
5 2Y
001aak023
Transparent top view
Fig 4. Pin configuration SOT996-2 (XSON8)
74HC3GU04
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 2 October 2013
© NXP B.V. 2013. All rights reserved.
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