BUK573-48C Datasheet, PDF (5/9 Pages) NXP Semiconductors – PowerMOS transistor Clamped logic level FET

Philips Semiconductors
PowerMOS transistor
Clamped logic level FET
Product specification
BUK573-48C
V(CL)DSR / V
51
BUK5Y3-48C
50
49
48
47
46
Tmb / degC =
45
150
44
25
-55
43
0
2
4
6
8
10
12
ID / A
Fig.9. Typical clamping voltage
V_(CL)DSR = f(I_D) ; conditions: R_G = 10 kΩ
a
1.5
Normalised RDS(ON) = f(Tj)
1.0
0.5
0
-60 -40 -20 0 20 40 60 80 100 120 140
Tj / C
Fig.10. Normalised drain-source on-state resistance.
a = R_DS(ON)/R_{DS(ON)25 ˚C} = f(T_j); I_D = 10 A; V_GS = 5 V
IS / A
40
Tmb / degC =
150
30 ²⁵
-55
20
BUK5Y3-48C
10
0
0
0.5
1
1.5
VSDS / V
Fig.11. Typical reverse diode current.
I_F = f(V_SDS); conditions: V_GS = 0 V; parameter T_j
V(CL)DSR / V
58
56
54
BUK5Y3-48C
Tmb / degC =
150
25
-55
52
50
48
46
44
1
2
5
10
20
RG / kOhm
Fig.12. Typical clamping voltgage
V_(CL)DSR = f(R_G) ; conditions: I_D = 10 A.
VGS(TO) / V
2
1
max.
typ.
min.
0
-60 -40 -20 0
20 40 60 80 100 120 140
Tj / C
Fig.13. Gate threshold voltage.
V_GS(TO) = f(T_j); conditions: I_D = 1 mA; V_DS = V_GS
ID / A
1E-01
SUB-THRESHOLD CONDUCTION
1E-02
1E-03
2%
typ
98 %
1E-04
1E-05
1E-06
0
0.4
0.8
1.2
1.6
2
2.4
VGS / V
Fig.14. Sub-threshold drain current.
I_D = f(V_GS); conditions: T_j = 25 ˚C; V_DS = V_GS
August 1994
5
Rev 1.000