BUK573-48C Datasheet, PDF (1/9 Pages) NXP Semiconductors – PowerMOS transistor Clamped logic level FET

Philips Semiconductors
PowerMOS transistor
Clamped logic level FET
Product specification
BUK573-48C
GENERAL DESCRIPTION
Protected N-channel enhancement
mode logic level field-effect power
transistor in a plastic full-pack
envelope.
The device is intended for use in
automotive applications. It has
built-in zener diodes providing active
drain voltage clamping.
PINNING - SOT186A
PIN
DESCRIPTION
1 gate
2 drain
3 source
case isolated
QUICK REFERENCE DATA
SYMBOL PARAMETER
MIN. TYP. MAX. UNIT
V_(CL)DSR
I_D
P_tot
W_DSRR
R_DS(ON)
Drain-source clamp voltage
Drain current (DC)
Total power dissipation
Repetitive clamped turn off
energy; T_j = 150˚C
Drain-source on-state
resistance; V_GS = 5 V
40 48 58 V
13 A
25 W
50 mJ
85 mΩ
PIN CONFIGURATION
SYMBOL
d
case
12 3
g
s
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
CONDITIONS
V_DS
V_DG
±V_GS
I_D
I_D
I_DM
P_tot
T_stg
T_j
Drain-source voltage
Drain-gate voltage
Gate-source voltage
Drain current (DC)
Drain current (DC)
Drain current (pulse peak
value)
Total power dissipation
Storage temperature
Junction Temperature
continuous
continuous
-
T_hs = 25 ˚C
T_hs = 100 ˚C
T_hs = 25 ˚C
T_hs = 25 ˚C
-
-
THERMAL RESISTANCES
SYMBOL PARAMETER
R_{th j-hs}
R_{th j-a}
Thermal resistance junction to
heatsink
Thermal resistance junction to
ambient
CONDITIONS
with heatsink compound
MIN.
-
-
-
-
-
-
-
- 55
- 55
MAX.
30
30
15
13
8.2
52
25
150
150
UNIT
V
V
V
A
A
A
W
˚C
˚C
MIN. TYP. MAX. UNIT
-
-
5 K/W
-
55
- K/W
August 1994
1
Rev 1.000