74HC40105 Datasheet, PDF (5/25 Pages) NXP Semiconductors – 4-bit x 16-word FIFO register

Philips Semiconductors
4-bit x 16-word FIFO register
Product specification
74HC/HCT40105
data moves through the FIFO to the
output stage, resulting in the DOR
flag pulsing HIGH and a shift-out of
data occurring. The SO control must
be made LOW before additional data
can be shifted-out (see Fig.10).
High-speed burst mode
If it is assumed that the
shift-in/shift-out pulses are not
applied until the respective status
flags are valid, it follows that the
shift-in/shift-out rates are determined
by the status flags. However, without
the status flags a high-speed burst
mode can be implemented. In this
mode, the burst-in/ burst-out rates are
determined by the pulse widths of the
shift-in/shift-out inputs and burst rates
of 35 MHz can be obtained. Shift
pulses can be applied without regard
to the status flags but shift-in pulses
that would overflow the storage
capacity of the FIFO are not allowed
(see Figs 11 and 12).
Expanded format
With the addition of a logic gate, the
FIFO is easily expanded to increase
word length (see Fig.17). The basic
operation and timing are identical to a
single FIFO, with the exception of an
additional gate delay on the flag
outputs. If during application, the
following occurs:
• SI is held HIGH when the FIFO is
empty, some additional logic is
required to produce a composite
DIR pulse (see Figs 7 and 18).
Due to the part-to-part spread of the
ripple through time, the SI signals of
FIFO_A and FIFO_B will not always
coincide and the AND-gate will not
produce a composite flag signal. The
solution is given in Fig.18.
The “40105” is easily cascaded to
increase the word capacity and no
external components are needed. In
the cascaded configuration, all
necessary communications and
timing are performed by the FIFOs.
The intercommunication speed is
determined by the minimum flag
pulse widths and the flag delays. The
data rate of cascaded devices is
typically 25 MHz. Word-capacity can
be expanded to and beyond 32-words
× 4-bits (see Fig.19).
1998 Jan 23
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