74HC40105 Datasheet, PDF (12/25 Pages) NXP Semiconductors – 4-bit x 16-word FIFO register

Philips Semiconductors
4-bit x 16-word FIFO register
Master reset applied with FIFO full
Product specification
74HC/HCT40105
Notes to Fig.8
1. DIR LOW, output ready HIGH;
assume FIFO is full.
2. MR pulse HIGH; clears FIFO.
3. DIR goes HIGH; flag indicates
input prepared for valid data.
4. DOR drops LOW; flag indicates
FIFO empty.
(1) HC : V_M = 50%; V_I = GND to V_CC.
HCT : V_M = 1.3 V; V_I = GND to 3 V.
Fig.8 Waveforms showing the MR input to DIR, DOR output
propagation delays and the MR pulse width.
Shifting out sequence; FIFO full to FIFO empty
(1) HC : V_M = 50%; V_I = GND to V_CC.
HCT : V_M = 1.3 V; V_I = GND to 3 V.
Fig.9 Waveforms showing the SO input to DIR output propagation
delay. The SO pulse width and SO maximum pulse frequency.
Notes to Fig.9
1. DOR HIGH; no data transfer in
progress, valid data is present at
output stage.
2. SO set HIGH.
3. SO is set LOW; data in the input
stage is unloaded, and new data
replaces it as empty location
“bubbles-up” to input stage.
4. DOR drops LOW; output stage
“busy”.
5. DOR goes HIGH; transfer
process completed, valid data
present at output after the
specified propagation delay.
6. Repeat process to unloaded the
3rd through to the 16th word from
FIFO.
7. DOR remains LOW; FIFO is
empty.
1998 Jan 23
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