74HC40105 Datasheet, PDF (13/25 Pages) NXP Semiconductors – 4-bit x 16-word FIFO register

Philips Semiconductors
4-bit x 16-word FIFO register
Product specification
74HC/HCT40105
With FIFO empty; SO is held HIGH in anticipation
agewidth
SI INPUT
2 VM ⁽¹⁾
SO INPUT
1
VM ⁽¹⁾
DOR OUTPUT
Qn OUTPUT
5
t _PLH
ripple through
delay
4
VM ⁽¹⁾
tPHL
6
t _PHL / t _PLH
3
MBA337
(1) HC : V_M = 50%; V_I = GND to V_CC.
HCT : V_M = 1.3 V; V_I = GND to 3 V.
Fig.10 Waveforms showing ripple through delay SI input to DOR output
and propagation delay from the DOR pulse to the Q_n output.
Notes to Fig.10
1. FIFO is initially empty, SO is held
HIGH.
2. SI pulse; loads data into FIFO
and initiates ripple through
process.
3. DOR flag signals the arrival of
valid data at the output stage.
4. Output transition; data arrives at
output stage after the specified
propagation delay between the
rising edge of the DOR pulse to
the Q_n output.
5. SO set LOW; necessary to
complete shift-out process. DOR
remains LOW, because FIFO is
empty.
6. DOR goes LOW; FIFO is empty
again.
Shift-in operation; high-speed burst mode
Note to Fig.11
In the high-speed mode, the burst-in
rate is determined by the minimum
shift-in HIGH and shift-in LOW
specifications. The DIR status flag is
a don’t care condition, and a shift-in
pulse can be applied regardless of the
flag. A SI pulse which would overflow
the storage capacity of the FIFO is
ignored.
(1) HC : V_M = 50%; V_I = GND to V_CC.
HCT : V_M = 1.3 V; V_I = GND to 3 V.
Fig.11 Waveforms showing SI minimum pulse width and SI maximum
pulse frequency, in high-speed shift-in burst mode.
1998 Jan 23
13