74HC40105 Datasheet, PDF (14/25 Pages) NXP Semiconductors – 4-bit x 16-word FIFO register

Philips Semiconductors
4-bit x 16-word FIFO register
Shift-out operation; high-speed burst mode
Product specification
74HC/HCT40105
In the high-speed mode, the burst-out rate is determined by the
minimum shift-out HIGH and shift-out LOW specifications. The
DOR flag is a don’t care condition and a SO pulse can be applied
without regard to the flag.
(1) HC : V_M = 50%; V_I = GND to V_CC.
HCT : V_M = 1.3 V; V_I = GND to 3 V.
Fig.12 Waveforms showing SO minimum pulse width and maximum pulse frequency, in high-speed shift-out
burst mode.
The shaded areas indicate when the input is permitted
to change for predictable output performance.
(1) HC : V_M = 50%; V_I = GND to V_CC.
HCT : V_M = 1.3 V; V_I = GND to 3 V.
Fig.13 Waveforms showing hold and set up times for D_n input to SI input.
(1) HC : V_M = 50%; V_I = GND to V_CC.
HCT : V_M = 1.3 V; V_I = GND to 3 V.
Fig.14 Waveforms showing SO input to Q_n output propagation delays and output transition time.
1998 Jan 23
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