74HC40105 Datasheet, PDF (17/25 Pages) NXP Semiconductors – 4-bit x 16-word FIFO register

Philips Semiconductors
4-bit x 16-word FIFO register
Product specification
74HC/HCT40105
Expanded format
Fig.19 shows two cascaded FIFOs providing a capacity of 32 words × 4 bits
Fig.20 shows the signals on the nodes of both FIFOs after the application of a SI pulse, when both FIFOs are initially
empty. After a rippled through delay, date arrives at the output of FIFO_A. Due to SO_A being HIGH, a DOR pulse is
generated. The requirements of SI_B and D_nB are satisfied by the DOR_A pulse width and the timing between the rising
edge of DOR_A and Q_nA. After a second ripple through delay, data arrives at the output of FIFO_B.
Fig.21 shows the signals on the nodes of both FIFOs after the application of a SO_R pulse, when both FIFOs are initially
full. After a bubble-up delay a DIR_R pulse is generated, which acts as a SO_A pulse for FIFO_A. One word is transferred
from the output of FIFO_A to the input of FIFO_B. The requirements of the SO_A pulse for FIFO_A is satisfied by the pulse
width of DOR_B. After a second bubble-up delay an empty space arrives at D_nA, at which time DIR_A goes HIGH.
Fig.22 shows the waveforms at all external nodes of both FIFOs during a complete shift-in and shift-out sequence.
The PC7HC/HCT40105 is easily cascaded to increase word capacity without any external circuitry. In cascaded format, all necessary
communications are handled by the FIFOs. Figs 17 and 19 demonstrate the intercommunication timing between FIFO_A and FIFO_B. Fig.22 gives an
overview of pulse and timing of two cascaded FIFOs, when shifted full and shifted empty again.
Fig.19 Cascading for increased word capacity; 32 words × 4 bits.
1998 Jan 23
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