74HC40105 Datasheet, PDF (18/25 Pages) NXP Semiconductors – 4-bit x 16-word FIFO register

Philips Semiconductors
4-bit x 16-word FIFO register
(1) HC : V_M = 50%; V_I = GND to V_CC.
HCT : V_M = 1.3 V; V_I = GND to 3 V.
Fig.20 FIFO to FIFO communication; input timing under
empty condition.
(1) HC : V_M = 50%; V_I = GND to V_CC.
HCT : V_M = 1.3 V; V_I = GND to 3 V.
Fig.21 FIFO to FIFO communication; output timing under
full condition.
1998 Jan 23
18
Product specification
74HC/HCT40105
Notes to Fig.20
1. FIFO_A and FIFO_B initially empty, SO_A held
HIGH in anticipation of data.
2. Load one word into FIFO_A; SI pulse applied,
results in DIR pulse.
3. Data out _A/data in _B transition; valid data
arrives at FIFO_A output stage after a specified
delay of the DOR flag, meeting data input
set-up requirements of FIFO_B.
4. DOR_A and SI_B pulse HIGH; (ripple through
delay after SI_A LOW) data is unloaded from
FIFO_A as a result of the data output ready
pulse, data is shifted into FIFO_B.
5. DIR_B and SO_A go LOW; flag indicates input
stage of FIFO_B is busy, shift-out of FIFO_A is
complete.
6. DIR_B and SO_A go HIGH automatically; the
input stage of FIFO_B is again able to receive
data, SO is held HIGH in anticipation of
additional data.
7. DOR_B goes HIGH; (ripple through delay after
SI_B LOW) valid data is present one
propagation delay later at the FIFO_B output
stage.
Notes to Fig.21
1. FIFO_A and FIFO_B initially empty, SI_B held
HIGH in anticipation of shifting in new data as
empty location bubbles-up.
2. Unload one word into FIFO_B; SO pulse
applied, results in DOR pulse.
3. DIR_B and SO_A pulse HIGH; (bubble-up delay
after SO_B LOW) data is loaded into FIFO_B as
a result of the DIR pulse, data is shifted out of
FIFO_A.
4. DOR_A and SI_B go LOW; flag indicates the
output stage of FIFO_A is busy, shift-in to
FIFO_R is complete.
5. DOR_A and SI_B go HIGH; flag indicates valid
data is again available at FIFO_A output stage,
SI_B is held HIGH, awaiting bubble-up of
empty location.
6. DIR_A goes HIGH; (bubble-up delay after
SO_A LOW) an empty location is present at
input stage of FIFO_A.