PCA5010 Datasheet, PDF (49/112 Pages) NXP Semiconductors – Pager baseband controller

Philips Semiconductors
Pager baseband controller
Product specification
PCA5010
Table 42 Description of the DMD1 bits
BIT
DMD1.7
DMD1.6
DMD1.5
DMD1.4
DMD1.3
DMD1.2
DMD1.1
DMD1.0
SYMBOL
ENA
AVG6
AVG5
AVG4
AVG3
AVG2
AVG1
AVG0
FUNCTION
enable averaging function/offset calculation
7-bit value indicating the offset value of the demodulator. This is an indication of the LO
offset frequency and will be used to determine the AFC output voltage. For coding see
Table 37.
6.17.4 CLOCK RECOVERY CONTROL REGISTER (DMD2)
The clock recovery control register DMD2 contains the control bits for enabling the clock recovery function and setting
its mode.
Whenever the clock recovery function is enabled (DMD2.7 = 1) the positive edge of the synchronized SYMCLK signal
will force a SymClk interrupt through the IRQ1.3 request flag after [B2, B1 and B0] received bits (see Table 50).
Table 43 Clock Recovery Control Register (DMD2, SFR address EEH)
7
6
5
4
3
2
1
0
ENC
−
BF
−
TEST
B2
B1
B0
Table 44 Description of the DMD2 bits
BIT
DMD2.7
DMD2.6
DMD2.5
DMD2.4
DMD2.3
DMD2.2
DMD2.1
DMD2.0
SYMBOL
ENC
−
BF
−
TEST
B2
B1
B0
FUNCTION
enable clock recovery function
not used
bypass demodulator filter
not used
reserved, should always be logic 0
select number of bits per interrupt:
If LEV = 0 then 000 = 1-bit, 001 = 2-bit to 111 = 8-bit
If LEV = 1 then 00X = 2-bit, 01X = 4-bit, 10X = 6-bit, 11X = 8-bit
6.17.5 DEMODULATOR DATA REGISTER (DMD3)
The demodulator data register DMD3 contains the (demodulated) recovered received symbols.
Table 45 Demodulator Data Register (DMD3, SFR address EFH)
7
6
5
4
3
2
1
0
D7
D6
D5
D4
D3
D2
D1
D0
1998 Nov 02
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