PCA5010 Datasheet, PDF (32/112 Pages) NXP Semiconductors – Pager baseband controller

Philips Semiconductors
Pager baseband controller
Product specification
PCA5010
6.11.2 CLOCK CORRECTION CONTROL REGISTER (CCON)
The CCON special function register is used to control the clock correction by software.
Table 20 Clock Correction Control Register (CCON, SFR address FCH)
7
6
5
4
3
2
ENB
PLUS
TEST
CIV17
CIV16
−
1
BYPASS
0
SET
Table 21 Description of the CCON bits
BIT
CCON.7
CCON.6
CCON.5
CCON.4
CCON.3
CCON.2
CCON.1
CCON.0
SYMBOL
ENB
PLUS
TEST
CIV17
CIV16
−
BYPASS
SET
FUNCTION
Enable clock correction. If ENB = 1 has been set, then correction is enabled and will
stay enabled even when the DC/DC converter is shut down and restarted.
± Sign for value. If PLUS = 1 then clock pulses are inserted, or else deleted.
Test signal, must always be logic 0 in normal mode. It is used during test to bypass the
first 9 FFs in the timing generator divider chain. If TEST = 1 the clock rate of the signals
9600 Hz and 256 Hz is doubled and the frequency on 16 Hz and 4 Hz is multiplied
by 300.
bit 17 of interval value, is used as extension of CC0 and CC1
bit 16 of interval value, is used as extension of CC0 and CC1
unused.
Test signal, must always be logic 0 in normal mode. It is used during test to generate
76.8 kHz on all outputs of the timing generator (4 Hz, 16 Hz, 256 Hz and 9600 Hz).
A load signal to the interval register. After a logic 0 to logic 1 transition of this bit the
value of ENB, PLUS, TEST, BYPASS and CIV are copied into the local latches with the
next 76.8 kHz clock pulse. A duration of one MOV instruction is long enough for the set
operation to complete. The SFR values must remain stable for at least one oscillator
period because the actual transfer happens synchronized with the local clock
(see Figs 16 and 18).
6.11.3 CLOCK CORRECTION INTERVAL REGISTERS (CC0 AND CC1)
The CC0 and CC1 special function registers (together with CCON.3 and CCON.4) are used to define the interval between
subsequent clock correction actions.
Table 22 Clock Correction Interval Register (CC0, SFR address FDH)
7
CIV7
6
CIV6
5
CIV5
4
CIV4
3
CIV3
2
CIV2
1
CIV1
0
CIV0
Table 23 Clock Correction Interval Register (CC1, SFR address FEH)
7
CIV15
6
CIV14
5
CIV13
4
CIV12
3
CIV11
2
CIV10
1
CIV9
0
CIV8
1998 Nov 02
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