PCA5010 Datasheet, PDF (33/112 Pages) NXP Semiconductors – Pager baseband controller

Philips Semiconductors
Pager baseband controller
6.11.4 EXAMPLE SEQUENCE TO SET ANOTHER CLOCK CORRECTION INTERVAL
Product specification
PCA5010
handbook, full pagewidth
PLUS, ENB
and CIV
SET
valid value in SFR
must stay valid for
one period of 76.8 kHz
MGR117
Fig.16 Sequence for setting the clock compensation.
MOV CC0, #(CIV7 to CIV0)
MOV CC1, #(CIV8 to CIV15)
MOV CCON, #D4H
MOV CCON, #D5H.
6.11.5 TIMING
Figures 17 and 18 demonstrate how the clock correction
works and how the access of the microcontroller is
synchronized to the local operation.
handbook, full pagewidth
Interval counter
76.8 kHz
38.4 kHz
CORR for
clock recovery
corrected
38.4 kHz
with PLUS = 1
corrected
38.4 kHz
with PLUS = 0
After (CIV) clock ticks of 76.8 kHz or 38.4 kHz one correction is made.
Fig.17 Operation of clock compensation.
MGR118
1998 Nov 02
33