PIP212-12M Datasheet, PDF(4/21 Page) NXP Semiconductors

English

English German Russian Spanish Italian Polish Chinese Japanese Korean French Portuguese	Language :

PIP212-12M Datasheet, PDF (4/21 Pages) NXP Semiconductors – DC-to-DC converter powertrain

◁

Philips Semiconductors

PIP212-12M

DC-to-DC converter powertrain

Table 2: Pin description â¦continued

Symbol Pin

Type Description

REG5V

O 5 V regulated supply output

DISABLE 55

I/O disable driver function (active LOW)

n.c.

6, 9

not connected

7. Functional description

7.1 Basic operation

conversion supply

control circuit supply

PWM input

VDDG

REG5V

VDDC

VDDO

CBP

VI PIP212-12M CBN

DISABLE

VSSC

VSSO

100 nF

Lout

output

Cout

signal ground power ground

03ao39

Fig 3. Simpliï¬ed functional block diagram of a synchronous DC-to-DC converter output

stage

The PIP212-12M combines two MOSFET transistors and a MOSFET driver in a thermally

enhanced low inductance package for use in high frequency and high efï¬ciency

synchronous buck DC-to-DC converters; see Figure 3. The two MOSFETs are connected

in a half bridge conï¬guration between VDDO and VSSO. The mid point of the two transistors

is VO which is connected to the output of a DC-to-DC converter via an inductor. A logic

HIGH signal on the VI pin causes the lower MOSFET to be switched off and the upper

MOSFET to be switched on. Current will then ï¬ow from the supply (VDDO), through the

upper MOSFET and the inductor (Lout) to the output.

A logic LOW signal on the VI pin causes the upper MOSFET to be turned off and the lower

MOSFET to be switched on. Current then ï¬ows from the power ground (VSSO), through

the lower MOSFET and the inductor (Lout), to the output. The output voltage is determined

by the ratio of time that the upper and lower MOSFETs conduct.

7.2 Undervoltage Lockout (UVLO)

The UVLO function ensures the correct operation of the control circuit during a power-up

and power-down sequence. Power to the control circuit is provided by the VDDC pin. This

voltage is internally monitored to ensure that if VDDC is below the UVLO threshold, the

DISABLE pin is internally pulled LOW and both MOSFETs are off. This is indicated by the

power ready (PRDY) ï¬ag, an open drain output that is pulled LOW whenever VDDC is

below the UVLO threshold.

9397 750 14586

Preliminary data sheet

Rev. 02 â 2 March 2005

4 of 21

▷