PHN405 Datasheet, PDF (3/12 Pages) NXP Semiconductors – 4 N-channel 60 mohm FET array enhancement mode MOS transistors

Philips Semiconductors
4 N-channel 60 mΩ FET array
enhancement mode MOS transistors
QUICK REFERENCE DATA
SYMBOL
V_DS
V_GS
V_GSth
I_D
R_DSon
P_tot
PARAMETER
drain-source voltage (DC)
gate-source voltage (DC)
gate-source threshold voltage
drain current (DC)
drain-source on-state resistance
total power dissipation
CONDITIONS
I_D = 1 mA; V_DS = V_GS
T_s = 80 °C
I_D = 2 A; V_GS = 10 V
T_s = 80 °C
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
PARAMETER
CONDITIONS
Per FET
V_DS
V_GS
I_D
I_DM
P_tot
drain-source voltage (DC)
gate-source voltage (DC)
drain current (DC)
peak drain current
total power dissipation
T_stg
storage temperature
T_j
operating junction temperature
Current monitor
I_M
monitor current (DC)
I_MM
peak monitor current
Source-drain diode
I_S
source current (DC)
I_SM
peak source current
T_s = 80 °C; note 1
note 2
T_s = 80 °C; note 3
T_s = 80 °C; note 4
T_s = 80 °C; note 5
T_s = 80 °C
note 2
T_s = 80 °C
note 2
Notes
1. T_s is the temperature at the soldering point of the drain lead.
2. Pulse width and duty cycle limited by maximum junction temperature.
3. When only one FET dissipates.
4. When either FETs 1 and 3 or 2 and 4 dissipate an equal amount of power.
5. When all four FETs dissipate an equal amount of power.
Product specification
PHN405
MIN.
−
−
1
−
−
−
MAX.
30
±20
2.8
3.7
60
1.4
UNIT
V
V
V
A
mΩ
W
MIN. MAX. UNIT
−
30
V
−
±20
V
−
3.7
A
−
14.8
A
−
1.4
W
−
1.25
W
−
1.09
W
−55
+150 °C
−55
+150 °C
−
50
mA
−
220
mA
−
1.4
A
−
5.6
A
1998 Mar 17
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