TDA4886A Datasheet, PDF (29/52 Pages) NXP Semiconductors – 140 MHz video controller with I2C-bus

Philips Semiconductors
140 MHz video controller with I²C-bus
Product specification
TDA4886A
Table 4 Subaddress and data byte format
FUNCTION
SUBADDRESS⁽¹⁾
DATA BYTE⁽²⁾
DIRECT
MODE
BUFFERED
MODE
D7⁽⁴⁾
D6⁽⁴⁾
D5⁽⁴⁾
D4⁽⁴⁾
D3⁽⁴⁾
D2⁽⁴⁾ D1⁽⁴⁾
D0⁽⁴⁾
NOMINAL
VALUE⁽³⁾
Control register
00H
80H
X⁽⁵⁾ X⁽⁵⁾ BLH2 BLH1 FPOL DISV DISO PEDST 08H
Brightness control 01H
81H
X⁽⁵⁾ X⁽⁵⁾ A15 A14 A13 A12 A11 A10
10H
Contrast control
02H
82H
X⁽⁵⁾ X⁽⁵⁾ A25 A24 A23 A22 A21 A20
26H
OSD contrast
control
03H
83H
X⁽⁵⁾ X⁽⁵⁾ X⁽⁵⁾ X⁽⁵⁾ A33 A32 A31 A30
0FH
Gain control
channel 1
04H
84H
X⁽⁵⁾ X⁽⁵⁾ A45 A44 A43 A42 A41 A40
3FH
Gain control
channel 2
05H
85H
X⁽⁵⁾ X⁽⁵⁾ A55 A54 A53 A52 A51 A50
3FH
Gain control
channel 3
06H
86H
X⁽⁵⁾ X⁽⁵⁾ A65 A64 A63 A62 A61 A60
3FH
Black level
07H
87H
A77 A76 A75 A74 A73 A72 A71 A70
−
reference channel 1
Black level
08H
88H
A87 A86 A85 A84 A83 A82 A81 A80
−
reference channel 2
Black level
09H
89H
A97 A96 A95 A94 A93 A92 A91 A90
−
reference channel 3
Notes
1. See Table 3 (Subaddress byte format).
2. The least significant bit (LSB) of an analog alignment register is defined as AX0 (data bit D0).
3. Under certain conditions the nominal values lead to nominal colour signals etc. (see note 3 of Chapter
“Characteristics”).
After power-up and after internal power-on reset of the I²C-bus the registers are set to the following values:
a) Control bit FPOL to logic 1.
b) Control bits BLH2, BLH1, DISV, DISO and PEDST to logic 0.
c) All other alignment registers to logic 0 (minimum value for control registers).
4. Data bit.
5. X means don’t care but for software compatibility with other video ICs with the same slave address, they are
preferably set to logic 0.
1998 Dec 04
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