TDA4886A Datasheet, PDF (18/52 Pages) NXP Semiconductors – 140 MHz video controller with I2C-bus

Philips Semiconductors
140 MHz video controller with I²C-bus
Product specification
TDA4886A
6. Pin 5 should be used for input clamping and blanking during vertical retrace (signal blanking, brightness blanking and
if control bit PEDST = 1 pedestal blanking). With a fast clamping pulse (transition between V₅ = 1.2 to 3.5 V and vice
versa in less than 75 ns/V) no blanking will occur during input clamping.
For 75 ns/V < t_r/f5 ≤ 280 ns/V the generation of the internal vertical blanking pulse is uncertain. For t_r/f5 > 280 ns/V
the internal blanking pulse will be generated.
Pin 5 open-circuited will activate permanent input clamping and undefined blanking.
7. Pin 5 can be used to synchronize all adjustments via the I²C-bus (one by one). In case of a completed I²C-bus
transmission in buffered mode only the leading edge of a vertical blanking pulse activates an adjustment. See also
Section 7.10.
After the adjustment has been activated (validation of buffered I²C-bus data) the I²C-bus will be reset and further
transmissions in direct or buffered mode are enabled.
I²C-bus transmissions in direct mode need no synchronization pulses.
8. Input voltages less than −0.1 V can produce internal substrate currents which disturb the leakage currents at the
signal inputs. An internal protection circuit creates a current for pin voltages of approximately 0 V or less. Feeding
clamping/blanking pulses via a resistor of some kΩ protects the pin from negative voltages.
9. Pin 11 should be used for output clamping and/or blanking. Pin 11 open-circuited will activate permanent blanking
and output clamping.
10. Composite signals will not disturb normal operations because an internal clipping circuit cuts all signal parts below
input reference black level (see Fig.3).
11. Contrast control acts on internal colour signals under I²C-bus control; subaddress 02H (bit resolution 1.6% of
contrast range).
12.
∆ G_track
=
20 × maximum of



log



A--A---₁^-1-₀^-
×
A--A---_2-2-0-



;
log



A--A---₁^-1-₀^-
×
A--A---_3-3-0-



;
log



A--A---₂^-2-₀^-
×
A--A---_{3-3-0- }

 dB

A_n: colour signal output amplitude in channel n = 1, 2 or 3 at any contrast setting.
A_n0: colour signal output amplitude in channel n = 1, 2 or 3 at nominal contrast setting and same gain setting.
13. When OSD fast blanking is active and V_2,3,4 are HIGH (V₁ > 1.7 V, V_2,3,4 > 1.7 V) the OSD colour signals will be
inserted in front of the gain potentiometers. This assures a correct grey scale of all video signals. The amplitudes of
the inserted OSD signals can be controlled simultaneously by OSD contrast via the I²C-bus.
14. OSD contrast control acts on inserted OSD colour signals under I²C-bus control; subaddress 03H (bit resolution
6.7% of OSD contrast range).
15. This pin can be used for subcontrast setting, beam current limiting and contrast modulation. Both the video and OSD
contrast are reduced simultaneously (see Figs 8 and 9). Because of the high-ohmic input impedance the pin should
be tied to a voltage of more than 5 V or applied with a capacitor of some nF if not used.
16. Brightness control adds an I²C-bus controlled DC offset to the internal colour signal; subaddress 01H (bit resolution
1.6% of brightness range).
17. The voltage difference between video black level and reference black level is related to the colour signal (see note 3)
with nominal 0.7 V (p-p) input signal, at nominal contrast (subaddress 02H = 26H) and for any gain setting.
The voltage difference (in Volts) is proportional to the gain setting (grey scale tracking). Therefore ∆V_bl (in percent)
is constant for any gain setting. The given values of ∆V_bl are valid only for video black levels higher than the signal
output switch-off voltage V_{22,19,16(min)}.
18. Gain control acts on video signals and inserted OSD video signals under I²C-bus control; subaddress 04H
(channel 1), 05H (channel 2) and 06H (channel 3; bit resolution 1.6% of gain range respectively).
1998 Dec 04
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