TDA4886A Datasheet, PDF (28/52 Pages) NXP Semiconductors – 140 MHz video controller with I2C-bus

Philips Semiconductors
140 MHz video controller with I²C-bus
Product specification
TDA4886A
Table 3 Subaddress byte format
FUNCTION
Control register
Brightness control
Contrast control
OSD contrast control
Gain control channel 1
Gain control channel 2
Gain control channel 3
Black level reference channel 1
Black level reference channel 2
Black level reference channel 3
SUBADDRESS⁽¹⁾
SUBADDRESS BYTE
DIRECT
MODE
BUFFERED
MODE
S7⁽²⁾
S6⁽²⁾
S5⁽²⁾
S4⁽²⁾
S3⁽²⁾
S2⁽²⁾
S1⁽²⁾
S0⁽²⁾
00H
80H
B⁽³⁾ 0
0
0
0
0
0
0
01H
81H
B⁽³⁾ 0
0
0
0
0
0
1
02H
82H
B⁽³⁾ 0
0
0
0
0
1
0
03H
83H
B⁽³⁾ 0
0
0
0
0
1
1
04H
84H
B⁽³⁾ 0
0
0
0
1
0
0
05H
85H
B⁽³⁾ 0
0
0
0
1
0
1
06H
86H
B⁽³⁾ 0
0
0
0
1
1
0
07H
87H
B⁽³⁾ 0
0
0
0
1
1
1
08H
88H
B⁽³⁾ 0
0
0
1
0
0
0
09H
89H
B⁽³⁾ 0
0
0
1
0
0
1
0AH to 0FH 8AH to 8FH not used
Notes
1. The most significant bit (MSB) of the subaddress enables an I²C-bus transmission in direct or in buffered mode
(see note 3). Subaddresses outside the ranges 00H to 0FH and 80H to 8FH are not used.
2. Subaddress bit.
3. Most significant bit of subaddress byte. I²C-bus transmission in direct mode: B = 0. I²C-bus transmission in
buffered mode: B = 1.
1998 Dec 04
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