TDA4886A Datasheet, PDF (19/52 Pages) NXP Semiconductors – 140 MHz video controller with I2C-bus

Philips Semiconductors
140 MHz video controller with I²C-bus
Product specification
TDA4886A
19. Pedestal blanking produces an ultra black level during blanking and output clamping which is the most negative
signal at the signal output pins. The reference black level which should correspond to the ‘extended cut-off voltage’
at the cathodes is approximately ∆V_{22,19,16(PED)} higher (see Fig.5). The use of pedestal blanking with AC-coupled
cathodes (control bit FPOL = 1) allows a very simple black level restoration with a DC diode clamp instead of a
complicated pulse restoration circuit.
20. DC load currents of signal outputs must not exceed maximum sink currents, otherwise signal distortions may occur.
21. The signal-to-noise ratio is calculated by the formula (range 1 to 120 MHz):
N-S-- ^{= 20 × log p----e---a----k------t-o-------pR---e--M-a----kS----v--v-a--a--l-lu-u--e--e---o--o--f-f--t-t-h-h--e-e----n-n---o-o--m-i-s---ie-n----ao---l-u--s-t--pi-g--u--n-t--a--v-l--o-o--l--tu-a--t--gp---eu---t---v---o----l-t--a---g---e-- dB}
22. Large output currents e.g. I_{22,19,16(M)(source)} lead to signal depending power dissipation in output transistors. Thermal
V_BE variation is compensated.
23. Following formula can be used to approximately determine the output rise/fall time for any other input rise/fall time:
t_{r2/f, measured}
=
t_r2/f
(22,19,16)
+


t_r2/f,
input
–
(
1
ns
)
2

24. Transient crosstalk between any two output pins:
a) Input conditions: any channel (channel A) with nominal input signal and 1 ns rise time. The inputs of the other
two channels are capacitively coupled to ground (channel B). Gain setting to maximum (3FH). Contrast setting to
nominal (26H). No limiting/modulation of contrast (V₂₄ ≥ 5 V)
b) Output conditions: black level set to approximately 0.77 V for each channel at signal outputs. Output signals
are V_A and V_B respectively
c) Transient crosstalk suppression: α_ct(tr) = 20 × log _V-V----^AB- dB
25. The internal feedback reference voltages are not influenced by the value of control bit PEDST but depend on the
individual adjustments via the I²C-bus, the selected feedback polarity (control bit FPOL = 0 or 1) and the selected
black level for positive feedback polarity (control bit FPOL = 1 and control bits BLH2 = 0 or 1 and BLH1 = 0 or 1):
Control bit FPOL = 0: the internal feedback reference voltage acts under I²C-bus control; subaddress 07H
(channel 1), 08H (channel 2) and 09H (channel 3; bit resolution 0.4% of voltage range). Rising values of the data
bytes, e.g. 00H to FFH, correspond to rising values of the resulting reference black levels at signal outputs
(pins 22, 19 and 16). The internal feedback reference voltages can be measured at feedback inputs
(pins 23, 20 and 17) during output clamping (V₁₁ > 3.5 V) in closed feedback loop. The feedback loop remains
operative at reference black levels between the specified values of V_{22,19,16(rbl)(min)} and V_{22,19,16(rbl)(max)}.
Control bit FPOL = 1: the internal feedback reference voltage can be measured at signal outputs
(pins 22, 19 and 16) during output clamping (V₁₁ > 3.5 V). By means of control bits BLH2 and BLH1 it is possible to
choose one of the four specified values between approximately 0.75 and 1.5 V. This facilitates the adaption to
different kinds of post amplifiers.
26. Slow variations of video supply voltage V_CRT will be suppressed at the CRT cathode by the clamping feedback loop.
A change of V_CRT with 5 V leads to a specified change of the cathode voltage.
27. The external reference voltages act under I²C-bus control for control bit FPOL = 1; subaddress 07H (FB/R₁), 08H
(FB/R₂) and 09H (FB/R₃; bit resolution 0.4% of voltage range).
28. All adjustments via the I²C-bus can be synchronized with vertical blanking pulse at pin CLI. This is called I²C-bus
transmission in buffered mode. The adjustments via the I²C-bus will take effect immediately in the so called direct
mode.
The timing of I²C-bus transmissions in buffered mode is related to the vertical blanking. See specification of pin 5
(vertical blanking input) and note 7.
1998 Dec 04
19