74HC4046A Datasheet, PDF (27/34 Pages) NXP Semiconductors – Phase-locked-loop with VCO

Philips Semiconductors
Phase-locked-loop with VCO
Product specification
74HC/HCT4046A
SUBJECT
PLL frequency
capture range
PHASE
COMPARATOR
PC1, PC2 or PC3
DESIGN CONSIDERATIONS
Loop filter component selection
(a) τ = R3 x C2 (b) amplitude characteristic (c) pole-zero diagram
A small capture range (2f_c) is obtained if 2f_c ≈ ^1-_π- 2πf_L ⁄ τ
Fig. 27 Simple loop filter for PLL without offset; R3 ≥ 500 Ω.
PLL locks on
harmonics at
centre frequency
noise rejection at
signal input
AC ripple content
when PLL is
locked
PC1 or PC3
PC2
PC1
PC2 or PC3
PC1
PC2
PC3
(a) τ1 = R3 x C2; (b) amplitude characteristic (c) pole-zero diagram
τ2 = R4 x C2;
τ3 = (R3 + R4) x C2
Fig.28 Simple loop filter for PLL with offset; R3 + R4 ≥ 500 Ω.
yes
no
high
low
f_r = 2f_i, large ripple content at φ_DEMOUT = 90°
f_r = f_i, small ripple content at φ_DEMOUT = 0°
f_r = f_i, large ripple content at φ_DEMOUT = 180°
1997 Nov 25
27