74HC4046A Datasheet, PDF (12/34 Pages) NXP Semiconductors – Phase-locked-loop with VCO

Philips Semiconductors
Phase-locked-loop with VCO
Product specification
74HC/HCT4046A
T_amb (°C)
TEST CONDITIONS
SYM-
BOL
PARAMETER
74HC
V_CC
+25
−40 to +85
UNIT
−40 to +125
(V)
V_I
OTHER
min. typ. max. min. max. min. max.
R₂
resistor range
3.0
300
3.0
300
3.0
300
C1
capacitor range
40
no
40
limit
40
V_VCOIN operating voltage 1.1
1.9
range at VCO_IN
1.1
3.4
1.1
4.9
kΩ 3.0
4.5
6.0
pF 3.0
4.5
6.0
V 3.0
4.5
6.0
note 1
over the range
specified for
R1; for linearity
see Figs 20
and 21
Note
1. The parallel value of R1 and R2 should be more than 2.7 kΩ. Optimum performance is achieved when R1 and/ or
R2 are/is > 10 kΩ.
Demodulator section
Voltages are referenced to GND (ground = 0 V)
T_amb (°C)
TEST CONDITIONS
SYMBOL PARAMETER
74HC
+25
−40 to+85 −40 to +125 ^{UNIT VCC OTHER}
V
min. typ. max. min. max. min. max.
R_S
V_OFF
R_D
resistor range
50
50
50
offset voltage
VCO_IN to V_DEMOUT
dynamic output
resistance at DEM_OUT
300
300
300
±30
±20
±10
25
25
kΩ 3.0 at R_S > 300 kΩ
4.5 ^{the leakage current can}
6.0 ^{influence VDEMOUT}
mV 3.0 V_I = V_VCOIN = 1/2 V_CC;
4.5 ^{values taken over}
6.0 ^{RS range; see Fig.15}
Ω 3.0 V_DEMOUT = 1/2 V_CC
4.5
25
6.0
1997 Nov 25
12