TDA8006 Datasheet, PDF (23/40 Pages) NXP Semiconductors – Multiprotocol IC Card coupler

Philips Semiconductors
Multiprotocol IC Card coupler
Product specification
TDA8006
Auxiliary RAM (MAR0, address C or D, write only;
MAR1, address E or F, write only; MRR, MWR,
address 8 or 9, read/write; all bits cleared after reset)
In order to store data, 1 kbyte of auxiliary RAM may be
accessed through the peripheral interface. The content of
the RAM is undefined after reset. Note that only AD3,
AD2 and AD1 must be programmed for addressing the
RAM register, allowing faster operations if needed.
There are two methods to address this memory:
• Random method: the low order address is written in
MAR0, and the high order address is written in MAR1.
A write operation to MWR will write the data at the
preselected address on the falling edge of EN, and a
read operation to MRR will load to port P4 the data that
is stored at the preselected address on the falling edge
of EN.
• Sequential method: once low order and high order
addresses are written in MAR0 and MAR1, every read
or write operation to MRR or MWR will increment the
address that is stored in MAR0 and MAR1. Thus it is
possible to read or write data strings within the auxiliary
RAM without rewriting the addresses between 2 data
bytes. The auto-increment feature is operational on the
whole length of the RAM. In case of overflow, the count
starts again at address 00H.
Output Ports Extension Register (PER, address 7,
write only; all bits cleared after reset)
In this register, the four low order bits control the activation
of the card. The four high order bits D4, D5, D6 and D7
each control auxiliary ±2 mA push-pull output ports, which
can be used for any purpose (LEDs, control signals, etc.).
The electrical state of a port is HIGH if the bit is LOW, and
LOW if the bit is HIGH. The bits are cleared after reset
making the ports HIGH.
Activation sequence
When the card is inactive, pins V_CC, CLK, RST and I/O are
LOW, having low impedance with respect to GND.
The step-up converter is stopped. The I/O is configured in
reception mode with a high impedance path to the
ISO 7816 UART. Any spurious pulses from the card during
power-up will have no effect until I/O is enabled. When
requirements are fulfilled (correct voltage supply, card
present, no hardware problems), the microcontroller may
initiate an activation sequence by setting bit CMDVCC
HIGH (t₀).
• The step-up converter starts (t₁)
• V_CC starts rising from 0 to 5 V or to 3 V with a controlled
rise time of typically 0.16 V/µs (t₂)
• I/O, contacts C4 and C8 buffers are enabled (t₃);
integrated pull-up resistors of 10 kΩ are connected to
V_CC
• CLK is sent to the card (t₄)
• RST buffer is enabled (t₅).
In order to allow a precise count of clock pulses during
ATR in manual mode, a defined time window (t₃/t₅) is
opened where the clock may be sent to the card using
RSTIN. Beyond this window, RSTIN does not respond to a
clock pulse, and only monitors the card’s RST contact.
In automatic mode (ATREN set HIGH), RST is monitored
by the TDA8006, RSTIN is inactive and CLK is output by
the TDA8006 at t₃. RST is LOW. If the card has not
responded within the period of 40100 CLK pulses for
versions C2 and C3 (45000 for version C1), RST is set
HIGH for a maximum of 40100 CLK pulses for versions
C2 and C3 (45000 for version C1).
It is also possible to customize the activation sequence by
keeping CLK STOP LOW with RSTIN LOW beyond t₅, and
then output CLK using the CLK configuration.
The sequencer is clocked by ¹â„₆₄f_INT which gives a time
interval T of typically 25 µs. Thus t₁ = 0 to ¹â„₆₄T, t₂ = t₁ + T,
t₃ = t₁ + 4T, t₄ = t₃ to t₅ and t₅ = t₁ + 7T.
2000 Feb 21
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