TDA8006 Datasheet, PDF (22/40 Pages) NXP Semiconductors – Multiprotocol IC Card coupler

Philips Semiconductors
Multiprotocol IC Card coupler
Product specification
TDA8006
UART Transmit Register (UTR; address 4; write only;
all bits cleared after reset)
Bits D7 to D0 are the data bits to be transmitted to the
card. Due to the automatic conversion performed by the
UART according to the convention detected during TS, the
controller must write the characters to send to the card in
direct convention. The character to be sent may be written
to the UTR as soon as bit TBE (Transmit Buffer Empty) is
set in the status register.
If writing to the UCR occurs after 12.5 ETU + GT after the
previous start bit, then the transmission starts on the rising
edge of EN during the write operation. If writing to the UCR
occurs before 12.5 ETU + GT after the previous start bit,
the UART waits until 12.5 ETU + GT after the previous
start bit before starting the transmission.
In protocol T = 0, if a parity error is signalled by the card,
the previous character must be rewritten to the UTR.
The UART will then wait 13 ETU after the start bit of the
previous character before restarting the transmission.
STATUS REGISTER AND INTERRUPTS
The ISO 7816 UART reports its activity to the
microcontroller through the UART status register, which
acts upon the interrupt line INT.
All bits except for D5 generate an interrupt on INT, if
enabled, when they are set. D0, D2, D3, D4, D6 and D7
are cleared on the rising edge of EN after a read operation
of the USR. D1 is cleared when the data in the reception
buffer has been read-out. D5 may be used to check the
card’s presence and also to determine the reason for an
emergency deactivation during a card’s session. In case of
Early Answer (EA) or Mute Card (MC) during automatic
ATR processing, the card is not automatically deactivated.
If enabled, an interrupt is generated, and the controller
then decides to deactivate or not.
Table 11 UART Status Register (USR; address 5; read only; all bits cleared after reset except for D5)
BIT
NAME
D0 TX Buffer Empty (TBE)
D1 RX Buffer Full (RBF)
D2 First Start Detect (FSD)
D3 Parity Error (PE)
D4 Early Answer (EA)
D5 OFF
D6 Off Interrupt (OFFI)
D7 Mute Card (MC)
DESCRIPTION
this bit is set when the UART has finished transmitting the data written in
the UTR (at 10.8 ETU) or on the rising edge of TRN; it is reset on the rising
edge of EN during a read status operation
this bit is set when the UART has finished receiving a character from the card
(at 10.5 ETU); it is reset on the falling edge of EN during the read status
operation
this bit is set on the falling edge of the first start bit if SS = 1; it is reset on the
rising edge of EN during a read status operation
this bit is set when a parity error has been detected by the UART in
transmission or in reception mode at the same time as TBE and RBF; it is
reset on the rising edge of EN during a read status operation
this bit is set if a start bit has been detected on I/O between the 200 and 400
first CLK pulses when the UART is configured in automatic ATR processing; it
is reset on the rising edge of EN during a read status operation
this bit is set if the card is present and reset if the card is not present;
if CMDVCC is set HIGH, it may also be reset if a hardware problem causing
an emergency deactivation sequence has occurred
this bit is set when OFF state has changed; it is reset on the rising edge of EN
during a read status operation
this bit is set if a card has not answered after 80200 CLK pulses for versions
C2 and C3 (90000 for version C1), when the ISO 7816 UART is configured in
automatic ATR processing; it is reset on the rising edge of EN during a read
status operation
2000 Feb 21
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