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TDA8006 Datasheet, PDF (14/40 Pages) NXP Semiconductors – Multiprotocol IC Card coupler | |||
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Philips Semiconductors
Multiprotocol IC Card coupler
Product speciï¬cation
TDA8006
Table 4 Register addresses
X = donât care.
AD3
0
0
0
0
0
0
0
0
0
0
1
1
1
1
AD2
0
0
0
0
1
1
1
1
1
1
1
1
0
0
AD1
0
0
1
1
0
0
0
0
1
1
0
1
0
0
AD0
0
1
1
1
0
0
1
1
0
1
X
X
X
X
R/W
REGISTER
PERIPHERAL
0 CCR (Clock Conï¬guration Register)
clock generator
0 PDR (Programmable Divider Register)
0 SOR (Synchronous Output Register) ISO 7816 UART
1 SIR (Synchronous Input Register)
0 UTR (UART Transmit Register)
1 URR (UART Receive Register)
1 USR (UART Status Register)
0 UCR (UART Conï¬guration Register)
0 GTR (Guard Time Register)
0 PER (Ports Extension Register)
on/off sequencer
0 MAR0 (Memory Address LOW)
auxiliary RAM
0 MAR1 (Memory Address HIGH)
0 MWR (Memory Write Register)
1 MRR (Memory Read Register)
Clock circuit
The microcontroller clock (OSC), the card clock (CLK), the
ISO 7816 UART clock, and the clock to the external world
(CLKOUT), are derived from the main clock signals (XTAL
from 4 to 20 MHz, or an external clock signal applied to
XTAL1), or the internal oscillator (fINT).
⢠Microcontroller clock (OSC): after power-on or reset, the
microcontroller is clocked at 1â8fINT. Then, the application
may decide to clock it at 1â2fINT, 1â2fxtal or fxtal.
All frequency changes are synchronous, thereby
ensuring no hang-up due to short spikes etc.
⢠Card clock (CLK): the application may send a clock
frequency of 1â2fxtal, 1â4fxtal, 1â8fxtal or 1â2fINT (â1.25 MHz),
or may stop the clock at HIGH or LOW. All transitions
are synchronous, ensuring correct pulse length during
start or change, in accordance with ISO 7816. After
power-on or reset, CLK is held LOW.
⢠External clock output (CLKOUT): CLKOUT is a
permanent clock output for external use. The following
frequencies are possible: fxtal, 1â2fxtal and 1â4fxtal.
All transitions are synchronous. After power-on or reset,
CLKOUT is fixed at 1â4fxtal.
⢠ISO 7816 UART clock: the clock to the ISO 7816 UART
is identical to the clock to the card (CLK).
To achieve the different I/O baud rates as defined by
values F and D (see Table 7), the clock signal is counted
by an auto-reload 8-bit programmable counter and then
divided by a 31 or 32 prescaler.
All these configurations are controlled by the clock
configuration register and by the programmable divider
register.
2000 Feb 21
14
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