TDA4858 Datasheet, PDF (16/44 Pages) NXP Semiconductors – Economy Autosync Deflection Controller (EASDC)

Philips Semiconductors
Economy Autosync Deflection Controller
(EASDC)
Product specification
TDA4858
SYMBOL
PARAMETER
CONDITIONS
MIN.
PLL2 phase detector [HFLB (pin 1) and HPLL2 (pin 31)]
∆φ_PLL2
t_d(HFLB)
V_PROT(HPLL2)
I_{charge(HPLL2)}
PLL2 control (advance of
maximum advance
36
horizontal drive with respect to _{minimum advance}
−
middle of horizontal flyback)
delay between middle of
horizontal sync and middle of
horizontal flyback
HPOS (pin 30) grounded −
maximum voltage for PLL2
−
protection mode/soft start
charge current for external
V_HPLL2 < 3.7 V
−
capacitor during soft start
HORIZONTAL FLYBACK INPUT [HFLB (PIN 1)]
V_HFLB
positive clamping level
I_HFLB = 5 mA
−
negative clamping level
I_HFLB = −1 mA
−
I_HFLB
positive clamping current
−
negative clamping current
−
V_HFLB
slicing level
−
Output stage for line driver pulses [HDRV (pin 7)]
OPEN COLLECTOR OUTPUT STAGE
V_HDRV
saturation voltage
I_{leakage(HDRV)}
output leakage current
AUTOMATIC VARIATION OF DUTY FACTOR
I_HDRV = 20 mA
I_HDRV = 60 mA
V_HDRV = 16 V
t_HDRV(OFF)/t_H
relative t_OFF time of HDRV
output; measured at
V_HDRV = 3 V; HDRV duty factor
is determined by the relation
I_HREF/I_VREF
I_HDRV = 20 mA;
f_H = 31.45 kHz; see Fig.9
I_HDRV = 20 mA;
f_H = 57 kHz; see Fig.9
I_HDRV = 20 mA;
f_H = 90 kHz; see Fig.9
X-ray protection [XRAY (pin 2)]
V_XRAY
t_W(XRAY)
R_I(XRAY)
V_RESET(VCC)
slicing voltage level
minimum width of trigger pulse
input resistance at XRAY
(pin 2)
supply voltage for reset of
X-ray latch
V_XRAY < 6.38 V + V_BE
V_XRAY > 6.38 V + V_BE
−
−
−
42
45
46.6
6.14
10
500
−
−
TYP.
−
7
200
4.4
15
5.5
−0.75
−
−
2.8
−
−
−
45
46.3
48
6.38
−
−
5
5.6
MAX.
−
−
−
−
−
−
−
6
−2
−
0.3
0.8
10
48
47.7
49.4
6.64
−
−
−
−
UNIT
%
%
ns
V
µA
V
V
mA
mA
V
V
V
µA
%
%
%
V
µs
kΩ
kΩ
V
1997 Oct 27
16