TDA4858 Datasheet, PDF (14/44 Pages) NXP Semiconductors – Economy Autosync Deflection Controller (EASDC)

Philips Semiconductors
Economy Autosync Deflection Controller
(EASDC)
Product specification
TDA4858
SYMBOL
PARAMETER
CONDITIONS
MIN. TYP.
VERTICAL SYNC OUTPUT AT VSYNC (PIN 14) DURING COMPOSITE SYNC AT HSYNC (PIN 15)
I_VSYNC
output current
during internal vertical
−0.7
−1.0
sync
V_VSYNC
internal clamping voltage level during internal vertical 4.4
4.8
sync
steepness of slopes
−
300
Automatic polarity correction for vertical sync
t_VSYNC(max)
maximum width of vertical sync
pulse
t_d(VPOL)
delay for changing polarity
Video clamping/vertical blanking output [CLBL (pin 16)]
t_clamp(CLBL)
V_clamp(CLBL)
width of video clamping pulse
top voltage level of video
clamping pulse
measured at V_CLBL = 3 V
TC_clamp
temperature coefficient of
V_clamp(CLBL)
steepness of slopes for
clamping pulse
R_L = 1 MΩ; C_L = 20 pF
V_blank(CLBL)
top voltage level of vertical
blanking pulse
note 1
t_blank(CLBL)
TC_blank
V_scan(CLBL)
width of vertical blanking pulse
temperature coefficient of
V_blank(CLBL)
output voltage during vertical
scan
I_CLBL = 0
TC_scan
I_sink(CLBL)
I_load(CLBL)
temperature coefficient of
V_scan(CLBL)
internal sink current
external load current
SELECTION OF LEADING/TRAILING EDGE TRIGGER FOR VIDEO CLAMPING PULSE
V_CLSEL
voltage at CLSEL (pin 10) for
trigger with leading edge of
horizontal sync
voltage at CLSEL for trigger
with trailing edge of horizontal
sync
t_d(clamp)
delay between leading edge of V_CLSEL > 7 V
horizontal sync and start of
horizontal clamping pulse
delay between trailing edge of
horizontal sync and start of
horizontal clamping pulse
V_CLSEL < 5 V
−
0.3
0.6
4.32
−
−
1.7
240
−
0.59
−
2.4
−
7
0
−
−
−
−
0.7
4.75
+4
50
1.9
300
+2
0.63
−2
−
−
−
−
300
130
MAX.
−1.35
5.2
−
300
1.8
0.8
5.23
−
−
2.1
360
−
0.67
−
−
−3.0
V_CC
5
−
−
UNIT
mA
V
ns/mA
µs
ms
µs
V
mV/K
ns/V
V
µs
mV/K
V
mV/K
mA
mA
V
V
ns
ns
1997 Oct 27
14