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TDA4858 Datasheet, PDF (15/44 Pages) NXP Semiconductors – Economy Autosync Deflection Controller (EASDC)
Philips Semiconductors
Economy Autosync Deflection Controller
(EASDC)
Product specification
TDA4858
SYMBOL
PARAMETER
CONDITIONS
MIN. TYP.
tclamp(max)
maximum duration of video
VCLBL = 3 V; VCLSEL > 7 V −
−
clamping pulse after end of
VCLBL = 3 V; VCLSEL < 5 V −
−
horizontal sync
ICLSEL
input current
VCLSEL < 5 V
VCLSEL > 7 V
−
−
−
−
PLL1 phase comparator and frequency-locked loop [HPLL1 (pin 26) and HBUF (pin 27)]
tHSYNC(max)
tlock(HPLL1)
VHPLL1
VHBUF
maximum width of horizontal
sync pulse (referenced to line
period)
total lock-in time of PLL1
control voltage
buffered f/v voltage at HBUF
(pin 27)
Iload(HBUF)
maximum load current
ADJUSTMENT OF HORIZONTAL PICTURE POSITION
fH < 45 kHz
fH > 45 kHz
notes 2 and 3
fH(min); note 4
fH(max); note 4
−
−
−
−
−
40
−
5.6
−
2.5
−
−
∆HPOS
IHPOS
Vref(HPOS)
Voff(HPOS)
horizontal shift adjustment
range (referenced to horizontal
period)
input current
reference voltage at input
picture shift is centred if HPOS
(pin 30) is forced to ground
IHSHIFT = 0
IHSHIFT = −135 µA
∆HPOS = +10.5%
∆HPOS = −10.5%
note 5
−
−
−110
−
−
0
−10.5
+10.5
−120
0
5.1
−
Horizontal oscillator [HCAP (pin 29) and HREF (pin 28)]
fH(0)
∆fH(0)
TC
fH(max)
VHREF
free-running frequency without
PLL1 action (for testing only)
spread of free-running
frequency (excluding spread of
external components)
temperature coefficient of
free-running frequency
maximum oscillator frequency
voltage at input for reference
current
RHBUF = ∞;
RHREF = 2.4 kΩ;
CHCAP = 10 nF; note 3
30.53 31.45
−
−
−100 0
−
−
2.43 2.55
MAX.
0.15
1.0
−20
±3
20
25
80
−
−
−4.0
−
−
−135
−
−
0.1
32.39
±3.0
+100
130
2.68
UNIT
µs
µs
µA
µA
%
%
ms
V
V
mA
%
%
µA
µA
V
V
kHz
%
10−6/K
kHz
V
1997 Oct 27
15