80CL410 Datasheet, PDF (11/28 Pages) NXP Semiconductors – Low voltage/low power single-chip 8-bit microcontroller with I2C

Philips Semiconductors
Low voltage/low power single-chip
8-bit microcontroller with I²C
Product specification
80CL410/83CL410
INTERRUPT SYSTEM
External events and the real-time-driven
on-chip peripherals require service by the
CPU asynchronous to the execution of any
particular section of code. To tie the
asynchronous activities of these functions to
normal program execution, a multiple-source,
two-priority level, nested interrupt system is
provided. The 8XCL410 acknowledges
interrupt requests from thirteen sources, as
follows:
– INT0 and INT1
– Timer 0 and timer 1
– I²C-bus serial I/O interrupt
– INT2 to INT9 (port 1)
Each interrupt vectors to a separate location
in program memory for its service routine.
Each source can be individually enabled or
disabled by corresponding bits in the internal
enable registers (IEN0, IEN1) The priority
level is selected via the interrupt priority
register (IP0, IP1). All enabled sources can
be globally disabled or enabled.
External Interrupts INT2–INT9
Port 1 lines serve an alternative purpose as
eight additional interrupts INT2–INT9. When
enabled, each of these lines can “wake-up”
the device from power-down mode. Using the
IX1 register, each pin may be initialized to
either active high or low. IRQ1 is the interrupt
request flag register. Each flag, if the interrupt
is enabled, will be set on an interrupt request
but it must be cleared by software.
IEN0 (A8H)
Interrupt enable register
7
6
5
43
21
0
EA — ES1 — ET1 EX1 ET0 EX0
Bit Symbol
Function
IEN0.7 EEA General enable/disable
control
0 = no interrupt is enabled
1 = any individually enabled
interrupt will be
accepted
IEN0.6 —
(unused)
IEN0.5 ES1 Enable I₂C SIO interrupt
IEN0.4 —
(unused)
IEN0.3 ET1 Enable Timer T1 interrupt
IEN0.2 EX1 Enable external interrupt 1
IEN0.1 ET0 Enable Timer T0 interrupt
IEN0.0 EX0 Enable external interrupt 0
IEN1 (E8H)
Interrupt enable register
7
6
5
43
21
0
EX9 EX8 EX7 EX6 EX5 EX4 EX3 EX2
Bit Symbol
Function
IEN1.7 EX9 Enable external interrupt 9
IEN1.6 EX8 Enable external interrupt 8
IEN1.5 EX7 Enable external interrupt 7
IEN1.4 EX6 Enable external interrupt 6
IEN1.3 EX5 Enable external interrupt 5
IEN1.2 EX4 Enable external interrupt 4
IEN1.1 EX3 Enable external interrupt 3
IEN1.0 EX2 Enable external interrupt 2
where 0 = interrupt disabled
1 = interrupt enabled
IP0 (B8H)
Interrupt priority register
7
6
5
43
21
0
— — PS1 — PT1 PX1 PT0 PX0
Bit
IP0.7
IP0.6
IP0.5
IP0.4
IP0.3
IP0.2
IP0.1
IP0.0
Symbol
Function
—
(unused)
—
(unused)
PS1 I₂C SIO interrupt
priority level
—
(unused)
PT1 Timer 1 interrupt
prioity level
PX1 External interrupt 1
priority level
PT0 Timer 0 interrupt
prioity level
PX0 External interrupt 0
priority level
IP1 (F8H)
Interrupt priority register
7
6
5
43
21
0
PX9 PX8 PX7 PX6 PX5 PX4 PX3 PX2
Bit
IP1.7
IP1.6
IP1.5
IP1.4
IP1.3
IP1.2
IP1.1
IP1.0
Symbol
Function
PX9 External interrupt 9 priority
level
PX8 External interrupt 8 priority
level
PX7 External interrupt 7 priority
level
PX6 External interrupt 6 priority
level
PX5 External interrupt 5 priority
level
PX4 External interrupt 4 priority
level
PX3 External interrupt 3 priority
level
PX2 External interrupt 2 priority
level
Interrupt priority is as follows:
0 – low priority
1 – high priority
IX1 (E9H)
Interrupt polarity register
7
6
5
4
3
21
0
IL9 IL8 IL7 IL6 IL5 IL4 IL3 IL2
Bit
IX1.7
IX1.6
IX1.5
IX1.4
IX1.3
IX1.2
IX1.1
IX1.0
Symbol
Function
IL9 External interrupt 9 polarity
level
IL8 External interrupt 8 polarity
level
IL7 External interrupt 7 polarity
level
IL6 External interrupt 6 polarity
level
IL5 External interrupt 5 polarity
level
IL4 External interrupt 4 polarity
level
IL3 External interrupt 3 polarity
level
IL2 External interrupt 2 polarity
level
Writing either a “1” or “0” to an IX1 register bit
sets the priority level of the corresponding
external interrupt to active High or Low,
respectively.
1995 Jan 20
11