PE3335 Datasheet, PDF(9/15 Page) Peregrine Semiconductor Corp. – 3000 MHz UltraCMOS™ Integer-N PLL for Low Phase Noise Applications

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PE3335 Datasheet, PDF (9/15 Pages) Peregrine Semiconductor Corp. – 3000 MHz UltraCMOS™ Integer-N PLL for Low Phase Noise Applications

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PE3335

Product Specification

input is âlowâ, serial input data (Sdata input), B0 to

B7, are clocked serially into the enhancement

The enhancement register is double buffered to

prevent inadvertent control changes during serial

loading, with buffer capture of the serially entered

data performed on the falling edge of E_WR

according to the timing diagram shown in Figure

5. After the falling edge of E_WR, the data provide

control bits as shown in Table 8 with bit

functionality enabled by asserting the Enh input

âlowâ.

Direct Interface Mode

Direct Interface Mode is selected by setting the

Bmode input âhighâ.

Counter control bits are set directly at the pins as

shown in Table 7. In Direct Interface Mode, main

counter inputs M7 and M8, and R Counter inputs

R4 and R5 are internally forced low (â0â).

Table 7. Primary Register Programming

Interface

Mode Enh

Parallel 1

Bmode Smode R5 R4 M8 M7 Pre_en M6 M5 M4 M3 M2 M1

0 M2_WR rising edge load

M1_WR rising edge load

M0 R3 R2 R1 R0 A3 A2 A1 A0

A_WR rising edge load

D0 D7 D6 D5 D4 D3 D2 D1 D0

Serial*

B10

B11

B12 B13 B14 B15 B16 B17 B18 B19

Direct

0 Pre_en M6 M5 M4 M3 M2 M1 M0 R3 R2 R1 R0 A3 A2 A1 A0

*Serial data clocked serially on Sclk rising edge while E_WR âlowâ and captured in secondary register on S_WR rising edge.

MSB (first in)

(last in) LSB

Table 8. Enhancement Register Programming

Interface

Mode Enh

Parallel 0

Serial*

Bmode Smode

Reserved

Power

down

Counter

load

E_WR rising edge load

MSEL

output

Prescaler

output

*Serial data clocked serially on Sclk rising edge while E_WR âhighâ and captured in the double buffer on E_WR falling edge.

fc, fp OE

MSB (first in)

(last in) LSB

Document No. 70-0049-02 â www.psemi.com

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