PE3335 Datasheet, PDF (3/15 Pages) Peregrine Semiconductor Corp. – 3000 MHz UltraCMOS™ Integer-N PLL for Low Phase Noise Applications

PE3335
Product Specification
Table 1. Pin Descriptions (continued)
Pin No.
(44-lead
PLCC)
Pin No.
(48-lead
QFN)
Pin
Name
Interface
Mode
Type
S_WR
Serial
Input
13
7
D4
Parallel
Input
M4
Direct
Input
Sdata
Serial
Input
14
8
D5
Parallel
Input
M5
Direct
Input
Sclk
Serial
Input
15
9
D6
Parallel
Input
M6
Direct
Input
FSELS Serial
Input
16
10
D7
Parallel
Input
Pre_en
Direct
Input
17
11
GND
ALL
FSELP Parallel
Input
18
12
A0
Direct
Input
Serial
Input
E_WR
19
13
Parallel
Input
A1
Direct
Input
M2_WR Parallel
Input
20
14
A2
Direct
Input
Serial,
21
15
Smode
Parallel
Input
A3
Direct
Input
22
16
Bmode
ALL
Input
23
17,18
VDD
ALL
(Note 1)
24
19
M1_WR Parallel
Input
25
20
A_WR
Parallel
Input
26
21
Hop_WR
Serial,
Parallel
Input
27
22
Fin
ALL
Input
Description
Serial load enable input. While S_WR is “low”, Sdata can be serially clocked.
Primary register data are transferred to the secondary register on S_WR or
Hop_WR rising edge.
Parallel data bus bit4
M Counter bit4
Binary serial data input. Input data entered MSB first.
Parallel data bus bit5.
M Counter bit5.
Serial clock input. Sdata is clocked serially into the 20-bit primary register
(E_WR “low”) or the 8-bit enhancement register (E_WR “high”) on the rising
edge of Sclk.
Parallel data bus bit6.
M Counter bit6.
Selects contents of primary register (FSELS=1) or secondary register
(FSELS=0) for programming of internal counters while in Serial Interface
Mode.
Parallel data bus bit7 (MSB).
Prescaler enable, active “low”. When “high”, Fin bypasses the prescaler.
Ground.
Selects contents of primary register (FSELP=1) or secondary register
(FSELP=0) for programming of internal counters while in Parallel Interface
Mode.
A Counter bit0 (LSB).
Enhancement register write enable. While E_WR is “high”, Sdata can be
serially clocked into the enhancement register on the rising edge of Sclk.
Enhancement register write. D[7:0] are latched into the enhancement register
on the rising edge of E_WR.
A Counter bit1.
M2 write. D[3:0] are latched into the primary register (R[5:4], M[8:7]) on the
rising edge of M2_WR.
A Counter bit2.
Selects serial bus interface mode (Bmode=0, Smode=1) or Parallel Interface
Mode (Bmode=0, Smode=0).
A Counter bit3 (MSB).
Selects direct interface mode (Bmode=1).
Same as pin 1 (MLP48 pin 43).
M1 write. D[7:0] are latched into the primary register (Pre_en, M[6:0]) on the
rising edge of M1_WR.
A write. D[7:0] are latched into the primary register (R[3:0], A[3:0]) on the
rising edge of A_WR.
Hop write. The contents of the primary register are latched into the
secondary register on the rising edge of Hop_WR.
Prescaler input from the VCO. 3.0 GHz max frequency.
Document No. 70-0049-02 │ www.psemi.com
©2005 Peregrine Semiconductor Corp. All rights reserved.
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