MN838898 Datasheet, PDF (8/20 Pages) Panasonic Semiconductor – CMOS LSI source driver for color TFT LCD panels

MN838898
　6.7 Cascade Connection
(1) RL = High
Driver A starts latching data one FY cycle after receiving a start pulse (STHR).
It asserts the carry signal (STHL) one FY cycle before latching the last data and then stopping.
MODE1 = High (360 outputs): 119 FY cycles
MODE1 = Low (324 outputs): 107 FY cycles
Cascade Connection
Driver B starts latching data one FY cycle after receiving the carry signal (STHL) from driver A.
Note: Although the carry signal (STHL) pulses are two FY cycles long, only the first cycle counts.
The next driver treats the two cycles as a single pulse.
FY
Pulse #1
Pulse #2
119 FY cycles (360 outputs)
1FY
1FY 1FY
DATA
LCD controller
6-bit RGB
data or 1-bit data
1 2 3 ････ 119 120 121 122 123 124
Data latched by driver A
Data latched by driver B
Start pulse
(1)
STHR
(2)
SRH L
STH R
STHL
Driver A
Driver B
Figure 6.7 Serial Cascade Connection
STHR
STHL
Driver C
(2) RL = Low
The start pulse input is from STHL; the carry output, from STHR. Apart from that, operation is the same
as for RL = High.
SDF00030AEM
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