MN838898 Datasheet, PDF (3/20 Pages) Panasonic Semiconductor – CMOS LSI source driver for color TFT LCD panels

MN838898
5. ₎Pin Descriptions
Pin Name
I/O
Direction
Table 5.1 Pin Descriptions
Pin Function
Description
DX0 to 5,
DY0 to 5,
DZ0 to 5
YX1 to 120,
YY1 to 120,
YZ1 to 120
Input
Gray scale digital data
input pins
Binary digital data
input pins
(DX5, DY5, and DZ5)
Input pins for gray scale (MODE2 = Low)
digital data, 6 bits each for R, G, and B.
DX5, DY5, and DZ5 represent the MSB;
DX0, DY0, and DZ0, the LSB.
Input pins for binary (MODE2 = High)
digital data, 1 bit each for R, G, and B.
Always drive the unused pins
(DX4 to DX0, DY4 to DY0, and DZ4 to DZ0)
at either High or Low level.
Output Analog image output pins These signals drive the LCD panel.
STH R, STHL
Start pulse I/O pins
I/O
These I/O pins are for the internal shift register's start pulses.
The following table indicates data shift direction by start pulses
during face up.
RL =H
RL =L
STHR Right shift input Left shift output
STHL Right shift output Left shift input
This specifies the shift direction: High level for right;
Low level for left.
RL
Input Shift direction input pin
H: Right shift input (YX,YY,YZ1 → 120)
L: Left shift input (YX,YY,YZ120 → 1)
FY
LD
INV
MODE1
MODE2
PS
NTEST
VREF_{0 to 10}
AV_DD, AV_SS
AV_DD1, AV_SS1
AV_DD2, AV_SS2
DV_DD, DV_SS
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Shift clock input pin
Data load input pin
Data inversion control
input pin
Number of drive outputs
select pin
Input format select pin
Power save function
select pin
Test input pin
(with built-in pull-up
resistance)
Gamma adjustment
potential input pin
Analog power supply
Analog power supply
Analog power supply
Digital power supply
This accepts the transfer clock for the shift register
High level input enables transfer, synchronized with rising
edges in the FY signal, of the LCD drive data from the built-
in DA converter.
The data logic when the INV input is at Low level is AVDD for Low
level and AVSS for High level. Driving INV at High level reverses
the data logic.
This specifies the number of LCD panel drive outputs:
High level for 360, Low level for 324, disabling
YX55 to YX66, YY55 to YY66, and YZ55 to YZ66.
(For further details, see Section 6.1 "Functional Description.")
This specifies the data input format: gray scale or binary.
High level: Binary. DX5, DY5, and DZ5 only. The DA
converter is off.
Low level: Gray scale. DX, DY, and DZ5
to DZ0. The DA converter is on.
High level input at a rising edge in the FY signal
cuts off current to outputs, fixing them
at high-impedance.
High level: High-impedance outputs. No current
to operational amplifier
or other components.
Low level: Normal operation
Normally fix this input at High level.
High level: Normal operation
Low level: Test mode
This input is the gamma adjustment potential input pin
for the DA converter.
This is the power supply for the DA converter's analog
circuits.
This is the power supply for the output analog circuits.
This is the power supply for the circuits protecting the output
circuits.
This is the power supply for the digital circuits.
SDF00030AEM
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