MN838898 Datasheet, PDF (6/20 Pages) Panasonic Semiconductor – CMOS LSI source driver for color TFT LCD panels

MN838898
6.3 Power Save Function
This signal can be switched anywhere except the latch signal, rising edges in the FY signal.
　
FY
LD
PS
YX01 to 120,
YY01 to 120,
YZ01 to 120
Hi-Z
Figure 6.3 High-Impedance Output Interval
6.4 Blanking Interval
The following timing chart summarizes the relationships between the load data
(LD) and start pulse (STHR and STHL) inputs and the blanking interval.
FY
Start pulse inputs
STHR (RL = High)
STHL (RL = Low)
2 FY (Min) _1FY
LD
1 FY (Max)
DX/DY/DZ0 to 5
N-4 N-3 N-2 N-1 N
1 234
2FY(Min)
Final data input Blanking interval
Figure 6.4 Blanking Interval
First data in1put for first line
6.5 Data Inverse Function
Driving the INV input at High level inverts all bits in the data input.
FY
DX 0 to 5
INV
Internal_{IDX0 to 5}
data
00 00 00 07 3F 3F 3F 00 00 05 08
3F 00 3F 07 3F 00 3F 00 00 05 08
Driving the INV input at High level inverts all bits in the data input.
Figure 6.5 Data Inverse Function
SDF00030AEM
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