MN838898 Datasheet, PDF (17/20 Pages) Panasonic Semiconductor – CMOS LSI source driver for color TFT LCD panels

MN838898
(2) AC Characteristics
DV_DD = 3.3V, AV_DD = 3.3V, AV_SS = DV_SS = 0 V, Ta = 25 °C
Rating
Item
Symbol Conditions
Unit
MIN TYP MAX
C24 _{FY period}
tp
Duty = 50 %
66.6
ns
C25 _{FY High level pulse width} t wcH
27
ns
C26 _{FY Low level pulse width} t wcL
27
ns
C27 Data/INV setup time
t st1
15
ns
C28 _{Data/INV hold time}
t hd1
15
ns
C29 Start pulse setup time
t st2
15
ns
C30 Start pulse hold time
t hd2
15
C31 Start pulse Low level pulse width
t _wsL
2
C32 _{Carry output delay time}
t d1
C_L = 15 pF
C33 LD signal High level pulse width
t _wldH
2
C34 LD signal Low level pulse width
t wldL
2
C35 LD signal-start pulse setup time
t _st3
2
C36 LD-FY setup time
t st4
15
C37 LD-FY hold time
t sd5
15
ns
FY period
40
ns
FY period
FY period
FY period
ns
ns
C38 MODE2 setup time
t st5 ^{Note 10)}
15
ns
C39 ^{MODE2 hold time}
C40 PS setup time
C41 PS hold time
C42 _{Data input invalid interval}
t hd5
t st6
t hd6
t ng1
Note 10)
15
15
15
1
C43 _{Final data timing}
t ng2
C44 LCD drive signal delay 1
C45 LCD drive signal delay 2
C46 LCD drive signal stop time
t d2
CL = 15 pF,
R=2KΩ, Note 10)
t _d3
C L ^{= 15 pF, R = 2KΩ,}
Note 11), Note 12)
t d4
CL = 15 pF,
R _{= 2KΩ}
ns
ns
ns
FY period
1 _{FY period}
20
µs
20
µs
5
µs
10) The reference point is the first FY rising edge after the rising edge in the start signal (STHR
or STHL).
11) This time is defined as that taken for the driver output voltage to reach, within 6-bit precision,
the target voltage.
12) The target output voltage shall be the output voltage just before the power save function takes
effectthat is, the latter shall be assumed to have reached the target.
· The above standards apply only to our standard package for the product.
SDF00030AEM
17