MN66279RSC Datasheet, PDF (70/96 Pages) Panasonic Semiconductor – LSI FOR COMPACT DISC/CD ROM PLAYER

MN662790RSC
7-2 (7) Digital PLL setting
For an improvement in playability of this LSI, a digital PLL circuit is built in so that the LSI will be in
stable operation without being influenced by digital noise. The lock range of this PLL circuit is not as wide
as an analog PLL circuit. Therefore, a system controller is required with an analog PLL circuit employed so
that the analog PLL circuit will be used in access operation and switched over to the digital PLL circuit at
the end of the access operation.
The digital PLL is available in normal- and 2x-speed playback modes.
The following mode combinations can be set.
Data Address
Function
D10
4E
Digital PLL operating
frequency
D7
Resolution
D6
VCO oscillation
frequency
Normal-speed playback
2x-speed playback
0 Ê·1 1 Ê·2 1 Ê·2 1 Ê·2
0 _1/8 1 _1/16 0 _1/8 1 _1/16
0 _{67 MHz} 0 _{67 MHz} 0 _{67 MHz} 1 _{138 MHz}
Use the SYFLG (i.e., the CLV synchronous establishment detecting flag) in the following sequence to switch
over the analog PLL circuit to digital PLL circuit.
Kick
Kick
ARF
Q read
Q read
Access end judgement
STAT (SYFLG)
IPFLAG
ɾɾɾɾɾɾ
Ë¢ SYFLG at H level
detected
Digital PLL set command issued
Note 1) Change the digital PLL circuit over to the analog PLL circuit at the start point of the access operation.
Change the digital PLL circuit over to the analog PLL circuit when the reading of the Q-code fails
while the LSI is in PLAY operation. Use a sequence like the one shown above to change the digital
PLL circuit over to the analog PLL circuit.
Note 2) The SYFLG can be used in playback mode after a short track jump, such as a single-track jump, or a
kick. In that case, make sure that the Q-code is read properly in a sequence like the one shown above
after the track jump or kick is performed.
SDD00025AEM
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