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MN66279RSC Datasheet, PDF (51/96 Pages) Panasonic Semiconductor – LSI FOR COMPACT DISC/CD ROM PLAYER
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MN662790RSC

Data (16 bits)ɹɹɹɹɹɹ
Address (8 bits)
Function (*: Setting at reset)
Ì­ D14 D13 Ì­ Ì­ Ì­ Ì­ Ì­ Ì­ Ì­ Ì­ Ì­ Ì­ Ì­ Ì­ Ì­
Ì­ 0 0 Ì­ Ì­ Ì­ Ì­ Ì­ Ì­ Ì­ Ì­ Ì­ Ì­ Ì­ Ì­Ì­
̭ 0 ̭̍ ̭ ̭ ̭ ̭ ̭ ̭ ̭ ̭ ̭ ̭ ̭̭
Ì­ 1 0 Ì­ Ì­ Ì­ Ì­ Ì­ Ì­ Ì­ Ì­ Ì­ Ì­ Ì­ Ì­Ì­
Ì­ 1 1 Ì­ Ì­ Ì­ Ì­ Ì­ Ì­ Ì­ Ì­ Ì­ Ì­ Ì­ Ì­Ì­
01000110
PLLF2 pin control (on-chip switch)
ˎ Forced OFF
Forced ON
ON with RESY set to "H"
ON with RESY set to "L"
D15 Ì­ Ì­ Ì­ Ì­ Ì­ Ì­ Ì­ Ì­ Ì­ Ì­ Ì­ Ì­ Ì­ Ì­ Ì­
PCK pin output mode
0 Ì­ Ì­Ì­ Ì­ Ì­ Ì­ Ì­ Ì­ Ì­ Ì­ Ì­ Ì­ Ì­ Ì­Ì­
ˎ PLL clock output
̭̍ ̭̭ ̭ ̭ ̭ ̭ ̭ ̭ ̭ ̭ ̭ ̭ ̭̭
DSL balance output

(F) Audio output control (III)ɹɹɹɹɹɹɹɹɹɹɹɹɹɹɹɹɹɹɹɹɹ
Table 7-1-4 (6)
Data (16 bits)ɹɹɹɹɹɹ
Address (8 bits)
Function (*: Setting at reset)
Ì­ Ì­ Ì­ Ì­ D11 Ì­ Ì­ Ì­ Ì­ Ì­ D5 Ì­ Ì­ Ì­ Ì­ D0 0 1 0 0 0 1 1 1
Ì­Ì­ Ì­Ì­ 0 Ì­ Ì­Ì­Ì­Ì­ 0 Ì­Ì­Ì­Ì­ 0
Ì­Ì­ Ì­Ì­ 0 Ì­ Ì­Ì­Ì­Ì­ 0 Ì­Ì­Ì­Ì­ 1
RFDET processing control of servo CPU
ˎ RFDET normal processing
Data processed as L-level signal
regardless of input
Ì­ Ì­ Ì­ Ì­ D11 Ì­ Ì­ Ì­ Ì­ Ì­ D5 Ì­ Ì­ Ì­ D1 Ì­
Ì­Ì­ Ì­Ì­ 0 Ì­ Ì­Ì­Ì­Ì­ 0 Ì­Ì­Ì­ 0 Ì­
Ì­Ì­ Ì­Ì­ 0 Ì­ Ì­Ì­Ì­Ì­ 0 Ì­Ì­Ì­ 1 Ì­
Ì­ Ì­ Ì­ Ì­ D11 Ì­ Ì­ Ì­ Ì­ Ì­ D5 Ì­ Ì­ D2 Ì­ Ì­
Ì­Ì­ Ì­ Ì­ 0 Ì­ Ì­ Ì­ Ì­ Ì­ Ì­ Ì­ Ì­ 0 Ì­Ì­
Ì­Ì­ Ì­ Ì­ 0 Ì­ Ì­ Ì­ Ì­ Ì­ Ì­ Ì­ Ì­ 1 Ì­Ì­
STAT output selection
(with output selected with MCLK)
ˎ OFF (Normal)
ON (FLOCK Ë  RFDET)
DSLBDA pin output mode
ˎ Not controlled
DSLB DAC output
Ì­ Ì­ Ì­ Ì­ D11 Ì­ Ì­ Ì­ Ì­ Ì­ D5 Ì­ D3 Ì­ Ì­ Ì­
Ì­Ì­ Ì­ Ì­ 0 Ì­ Ì­ Ì­ Ì­ Ì­ 0 Ì­ 0 Ì­ Ì­Ì­
Ì­Ì­ Ì­ Ì­ 0 Ì­ Ì­ Ì­ Ì­ Ì­ 0 Ì­ 1 Ì­ Ì­Ì­
SUBQ output control (SSELʹH)
ˎ MSB-first output
LSB-first output in the unit of byte
Ì­ Ì­ Ì­ Ì­ D11 Ì­ Ì­ Ì­ Ì­ Ì­ D5 D4 Ì­ Ì­ Ì­ Ì­
Ì­Ì­ Ì­ Ì­ 0 Ì­ Ì­ Ì­ Ì­ Ì­ 0 0 Ì­ Ì­ Ì­Ì­
Ì­Ì­ Ì­ Ì­ 0 Ì­ Ì­ Ì­ Ì­ Ì­ 0 1 Ì­ Ì­ Ì­Ì­
Oscillation stop control (See Note.)
ˎ Normal
Oscillation stop
Ì­ Ì­ Ì­ Ì­ D11 Ì­ Ì­ Ì­ Ì­ D6 D5 Ì­ Ì­ Ì­ Ì­ Ì­
Ì­Ì­ Ì­ Ì­ 0 Ì­ Ì­ Ì­ Ì­ 0 0 Ì­ Ì­ Ì­ Ì­Ì­
̭̭ ̭ ̭ 0 ̭ ̭ ̭ ̭ ̍ 0 ̭ ̭ ̭ ̭̭
DSL balance compensation circuit setting
ˎ Operation stop (with output on hold)
ɹ Compensation value retrieval
Ì­ Ì­ Ì­ Ì­ D11 Ì­ Ì­ Ì­ D7 Ì­ D5 Ì­ Ì­ Ì­ Ì­ Ì­
Ì­Ì­ Ì­ Ì­ 0 Ì­ Ì­ Ì­ 0 Ì­ 0 Ì­ Ì­ Ì­ Ì­Ì­
̭̭ ̭ ̭ 0 ̭ ̭ ̭ ̍ ̭ 0 ̭ ̭ ̭ ̭̭
TRV pin intermittent drive control
ˎ Normal mode (continuous drive)
Intermittent drive (at 44.1 kHz)
Ì­ Ì­ Ì­ Ì­ D11 Ì­ Ì­ D8 Ì­ Ì­ D5 Ì­ Ì­ Ì­ Ì­ Ì­
Ì­Ì­ Ì­ Ì­ 0 Ì­ Ì­ 0 Ì­ Ì­ 0 Ì­ Ì­ Ì­ Ì­Ì­
̭̭ ̭ ̭ 0 ̭ ̭ ̍ ̭ ̭ 0 ̭ ̭ ̭ ̭̭
DSL offset function with Tr OFF
ˎ With DSL offset
With no DSL offset
Ì­ Ì­ Ì­ Ì­ D11 Ì­ D9 Ì­ Ì­ Ì­ D5 Ì­ Ì­ Ì­ Ì­ Ì­
Ì­Ì­ Ì­ Ì­ 0 Ì­ 0 Ì­ Ì­ Ì­ 0 Ì­ Ì­ Ì­ Ì­Ì­
Ì­Ì­ Ì­ Ì­ 0 Ì­ 1 Ì­ Ì­ Ì­ 0 Ì­ Ì­ Ì­ Ì­Ì­
LSI clock control
ˎ Clock enabled
ɹ Clock disabled
Ì­ Ì­ Ì­ Ì­ D11 D10 Ì­ Ì­ Ì­ Ì­ D5 Ì­ Ì­ Ì­ Ì­ Ì­
Ì­Ì­ Ì­ Ì­ 0 0 Ì­ Ì­ Ì­ Ì­ 0 Ì­ Ì­ Ì­ Ì­Ì­
Ì­Ì­ Ì­ Ì­ 0 1 Ì­ Ì­ Ì­ Ì­ 0 Ì­ Ì­ Ì­ Ì­Ì­
Power down control
ˎ Not controlled
ɹ VCO, A/D, DF/DAC disabled
Note) Oscillation stop control can be reset with RST.
SDD00025AEM
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