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MN66279RSC Datasheet, PDF (7/96 Pages) Panasonic Semiconductor – LSI FOR COMPACT DISC/CD ROM PLAYER
MN662790RSC
No. Symbol
45 IREF
46 DRF
47 DSLF
48 PLLF
49 VCOF
50 AVDD2
51 AVSS2
52 EFM/
CK384
PCK/
53 DSLB
54 VCOF2
55 SUBC
56 SBCK
57 VSS
58 X1
59 X2
60 VDD
61 BYTCK/
TRVSTP
GIO1/
62 CLDCK
GIO2/
63 FCLK
64 IPFLAG
65 FLAG
Pin for
I/O 5-V input
I
Reference current input pin
Function
I
Bias pin for DSL
I/O
DSL loop filter pin
I/O
PLL loop filter pin
I/O
I
I
O
O
I/O
O
I
˓
I
I
O
I
O
O
O
O
O
VCO loop filter pin
Power supply for analog circuits
(For DSL, PLL, D/A output stage and A/D)
Ground for analog circuits (For DSL, PLL, D/A output stage and A/D)
At IOSEL = H: EFM signal output
At IOSEL = L: 16.9344-MHz clock output for crystal oscillation
384fS output for signal processing (VCO clock output in jitter-free
operation)
(Select crystal oscillation or signal processing with command setting)
PLL extraction clock output or DSL balance output (PWM output)
(fPCK=4.3218 MHz)
VCO loop filter pin for the digital servo clock generation at 33.8688 MHz
The external circuit is required for crystal oscillation at 16.9344 MHz.
Subcode serial output
In CD-TEXT 1 mode: TEXT data output
Clock input for subcode serial output
In CD-TEXT 1 mode: Clock input for TEXT data reading
Ground for oscillation circuit
Crystal oscillation circuit input pin (fʹ16.9344 MHz, 33.8688 MHz)
Crystal oscillation circuit output pin (fʹ16.9344 MHz, 33.8688 MHz)
Power supply for oscillation circuit
At IOSEL = H: Byte clock signal output
At IOSEL = L: Traverse stop signal output H: STOP mode
At default value:
General-purpose I/O port
At command execution: Subcode frame clock signal output (fCLDCK=7.35 kHz)
At default value:
General-purpose I/O port
At command execution: Crystal frame clock signal output (fFCLK=7.35 kHz)
Interpolation flag signal output
H: Interpolation
Flag signal output
SDD00025AEM
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