MN66279RSC Datasheet, PDF (59/96 Pages) Panasonic Semiconductor – LSI FOR COMPACT DISC/CD ROM PLAYER

MN662790RSC
7-2 (2) Serial data output with de-emphasis function ON
t
R-ch
L-ch
LRCK
BCLK
SRDATA
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Disabled data _MSB
LSB ^MSB
(0.75t) Disabled data
LSB ^Disabled
(0.75t) data


Figure 7-2-3 LRCK, BCLK and SRDATA output timing with de-emphasis function ON
The SRDATA signal is output at 32 fs and the LSB data after each LRCK change includes 0.25t disabled data.
The phase relation with the IPFLAG is not guaranteed.ɹɹɹɹɹɹɹɹɹ


7-2 (3) Serial data input format
The input data for the DF + DAC section can be given from the outside by setting the IOSEL pin to the L
level. When this is done, give an LRCK input through the MSEL pin, BCLK input through the SSEL pin and
SRDATA input through the PSEL pin. At this time, the internal settings of the conventional MSEL, SSEL and
PSEL pins will be MSEL = L, SSEL = H and PSEL = L, respectively.
ɾThe LRCK input frequency is fixed at 44.1 kHz. When the 2x-speed mode or jitter-free is used, a serial
data input is not available in other than the DF/DAC clock fixed mode, because the performance of a
D/A converter audio output is not assured. (See Table 7-1-38.)
ɾThe BCLK input can be arbitrarily set between 16 and 32 clocks per half an LRCK cycle. However,
ɹɹ LRCK should be changed synchronously with the falling edge of BCLK.
ɾThe SRDATA input is an MSB-first, 2's complement type input. It should be changed synchronously
with the falling edge of BCLK. Also, check that the contents of the SRDATA are L-ch data when
LRCK is at the H level.
As described above, the number of BCLK clocks can be 17 or more for each sampled data. If this is the
case, the contents of the SRDATA should be back-aligned with respect to an LRCK change point, and
LRCK must change before the rising edge of the next BCLK signal, after sampling the LSB of the
SRDATA at the rising edge of BCLK.
ɾD/A converter output muting, D/A converter output polarity switching, emphasis control and peak
detection DF output mode can be applied to a serial data input from an external source.
Bilingual switching only works on a serial data output, not on a serial data input.
SDD00025AEM
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