MN101EFA6 Datasheet, PDF (5/33 Pages) Panasonic Semiconductor – 8-bit Single-chip Microcontroller

MN101EFA6/A5/A1/A0 Series
8-bit Single-chip Microcontroller
PubNo. 216A6-012E
(Triangle wave and saw tooth wave are supported, dead time insertion available)
- Clock source
fpll-div, fpll-div/2, fpll-div/4, fpll-div/16, fs, fs/2, fs/4, fs/16,
Timer A divided by 1, 2, 4, 16, External clock divided by 1, 2, 4, 16
Timer A (Baud rate timer)
- Clock output for peripheral functions
- Clock source
fpll-div, fpll-div/2, fpll-div/4, fpll-div/8, fpll-div/16, fpll-div/32, fs/2, fs/4
- Watchdog timer
Time-out cycle can be selected from fs/2¹⁶, fs/2¹⁸, fs/2²⁰
On detection of 2 errors, forcibly hard reset inside LSI.
Operation start timing is selectable. (At reset release or write to register)
- Buzzer Output/ Reverse Buzzer Output
Output frequency can be selected from fpll-div/2⁹, fpll-div/2¹⁰, fpll-div/2¹¹, fpll-div/2¹², fpll-div/2¹³,
fpll-div/2¹⁴
- A/D Converter: 10-bit  12 channels (MN101EFA6/A1)
10-bit  8 channels (MN101EFA5/A0)
- Serial Interface: 3 channels (MN101EFA6/A1)
2 channels (MN101EFA5/A0)
Serial 0: UART (full duplex)/ Clock synchronous
Clock synchronous serial interface
- Transfer clock source fpll-div/2, fpll-div/4, fpll-div/16, fpll-div/64, fs/2, fs/4,
Timer 0 to 2 or Timer A divided by 1, 2, 4, 8, 16, External clock
- MSB/LSB can be selected as the first bit to be transferred,
arbitrary sizes of 1 to 8 bits are selectable.
- Sequence transmission, reception or both are available
Full duplex UART
- Baud rate timer, selected from Timer 0 to 2 or Timer A
- Parity check, overrun error/ framing error detection
- Transfer size 7 to 8 bits can be selected
Serial 1: UART (full duplex)/ Clock synchronous (MN101EFA5/A0 don't have this function)
Clock synchronous serial interface
- Transfer clock source fpll-div/2, fpll-div/4, fpll-div/16, fpll-div/64, fs/2, fs/4,
Timer 0 to 2 or Timer A divided by 1, 2, 4, 8, 16, External clock
- MSB/LSB can be selected as the first bit to be transferred,
arbitrary sizes of 1 to 8 bits are selectable.
- Sequence transmission, reception or both are available.
Full duplex UART
- Baud rate timer, selected from Timer 0 to 2 or Timer A
- Parity check, overrun error/ framing error detection
-Transfer size 7 to 8 bits can be selected
Serial 4: Multi master IIC/ Clock synchronous
Clock synchronous serial interface
- Transfer clock source fpll-div/2, fpll-div/4, fpll-div/16, fpll-div/32, fs/2, fs/4,
Publication date: November 2014