MN101EFA6 Datasheet, PDF (15/33 Pages) Panasonic Semiconductor – 8-bit Single-chip Microcontroller

1.3.3 Pin Functions
MN101EFA6/A5/A1/A0 Series
8-bit Single-chip Microcontroller
PubNo. 216A6-012E
Pins
VDD5
VSS
VDD18
MN101EF
A6/A1
48pin 44pin
TQFP QFP
MN101EF
A5/A0
I/O
32pin 32pin
SSOP TQFP
5
5
6
3
-
12
11
12
9
-
7
7
8
5
-
Function
Power connect pins
Internal power output pin
OSC1
11
10
11
8
OSC2
10
9
10
7
Input High speed operation clock input pin
Output High speed operation clock output pin
NRST
16
15
16
13
I/O
Reset pins [Active low]
ATRST 6
6
7
4
Input Auto reset setting pin
P00
18
16
17
14
I/O
I/O port 0
P01
19
17
18
15
P02
20
18
19
16
P03
21
19
20
17
P04
22
20
21
18
P05
23
21
22
19
P06
24
22
23
20
P07
25
23
24
21
P20
26
24
25
22
I/O
I/O port 2
P21
27
25
26
23
P22
28
26
27
24
P23
29
27
28
25
P24
30
28
-
-
P25
11
10
11
8
P26
10
9
10
7
P27
16
15
16
13
Input Input port 2
P30
13
12
13
10
I/O
I/O port 3
P31
14
13
14
11
P32
31
29
-
-
P33
32
30
-
-
P34
33
31
-
-
P35
34
32
-
-
P36
35
33
-
-
P40
36
34
-
-
I/O
I/O port 4
P41
37
35
-
-
P42
40
36
-
-
P43
41
37
-
-
P44
42
38
-
-
P45
43
39
-
-
Table remarks -: Without function
Description
Apply 4.0 V to 5.5 V to VDD5 and 0 V to VSS connect 0.1 F + 1 F
or larger bypass capacitor for internal power stabilization.
This pin is output 1.8 V from internal power circuit. Don’t use the
power supply to external device. For internal power circuit output sta-
bility, connect at least 0.1 F + 1 F one bypass capacitor between
VDD18 and VSS.
Connect these oscillation pins to ceramic or crystal ocsillators for
high-frequency clock operation.
If the clock is an external input, connect it to OSC1 and leave OSC2
open. The chip will not operate with an external clock when using
STOP mode.
This pin resets the chip when power is turned on, is allocated as P27
and contains an internal pull-up resistor (Typ. 50 k). Setting this pin
low initialize the internal state of the device.
Thereafter, setting the input to high releases the reset. The hardware
waits for the system clock to stabilize, then processes the reset inter-
rupt.
If a capacitor is to be inserted between NRST and VSS, it is recom-
mended that a discharge diode be placed between NRST and
VDD5.
Input "High" to enable auto reset function and “Low” to disable this
function
8-bit CMOS tri-state I/O port.
Each bit can be set individually as either an input or output by P0DIR
register. A pull-up resistor for each bit can be selected individually by
P0PLU register.
Direct LED drive is available at output.
At reset, the input mode is selected and pull-up resistor is disabled
(high impedance).
7-bit CMOS tri-state I/O port.
Each bit can be set individually as either an input or output by P2DIR
register. A pull-up resistor for each bit can be selected individually by
P2PLU register.
At reset, the input mode is selected and pull-up resistor is disabled
(high impedance)
P27 has an N-channel open-drain configuration.
7-bit CMOS tri-state I/O port.
Each bit can be set individually as either an input or output by P3DIR
register. A pull-up resistor for each bit can be selected individually by
P3PLU register.
At reset, the input mode is selected and pull-up resistor is disabled
(high impedance).
6-bit CMOS tri-state I/O port.
Each bit can be set individually as either an input or output by P4DIR
register. A pull-up /pull-down resistor for each bit can be selected
individually by P4PLUD register.
A pull-up/down resistor connection for each port can be selected
individually in SELUD register. A pull-up/pull down can not be mixed.
At reset, the input mode is selected and pull-up resistor is disabled
(high impedance).
Publication date: November 2014