N34TS04 Datasheet, PDF (9/18 Pages) ON Semiconductor – Digital Output Temperature Sensor

N34TS04
Table 9a. SWP SET COMMAND DETAIL (following Slave Address)
Command
Block(x)
Protection
Slave
Response
Address
Byte
Slave
Response
SWPx(Note 11)
Not Set
ACK
(Dummy)
ACK
Set
NoACK
(Dummy)
NoACK
CWP
X
ACK
(Dummy)
ACK
Data Byte
(Dummy)
(Dummy)
(Dummy)
Slave
Response
ACK
NoACK
ACK
Write
Cycle
Yes
No
Yes
Table 9b. SWP QUERRY COMMAND DETAIL (following Slave Address)
Command
Block(x)
Protection
Slave
Response
Data Byte
Master
(Response)
RPSx (Nots 11, 12)
Not Set
ACK
Dummy
(NoACK)
Set
NoACK
Dummy
(NoACK)
Data Byte
Dummy
Dummy
Master
(Response)
(NoACK)
(NoACK)
Table 9c. SPD PAGE SELECT COMMAND DETAIL (following Slave Address)
Command
SPD Active
Page
Slave
Response
Address
Byte
Slave
Response
SPAx (Notes 13, 14)
X
ACK
(Dummy)
ACK
Data Byte
(Dummy)
Slave
Response
NoACK
Write
Cycle
No
Table 9d. SPD ACTIVE PAGE QUERRY COMMAND DETAIL (following Slave Address)
Command
SPD Active
Page
Slave
Response
Data Byte
Master
(Response)
Data Byte
Master
(Response)
RPA (Notes 11, 12,
0
15)
1
ACK
NoACK
Dummy
Dummy
(NoACK)
(NoACK)
Dummy
Dummy
(NoACK)
(NoACK)
11. The Master can terminate the sequence by issuing a STOP once the N34TS04 responds with NoACK
12. The Master can terminate the sequence by responding with (NoACK) followed by STOP after any dummy data byte.
13. Setting the SPD Page Address to ‘0’ selects the lower 2−Kb EEPROM bank, setting it to ‘1’ selects the upper 2−Kb EEPROM bank.
14. The lower 2−Kb EEPROM bank (corresponding to SPD page address ‘0’) is active (visible) immediately following power−up.
15. The device will respond with ACK when the lower 2−Kb EEPROM bank is active and with NoACK when the upper 2−Kb EEPROM bank is
active.
BUS ACTIVITY: S
T
A
MASTER ^R
T
SDA LINE
SLAVE
ADDRESS
Dummy
ADDRESS
S
Dummy
T
DATA
O
P
SLAVE
X = Don’t Care
AN
C or O
KA
C
K
AN
C or O
KA
C
K
AN
C or O
KA
C
K
Figure 13. SWP & SPA Timing
BUS ACTIVITY: S
T
A
MASTER ^R
T
SDA LINE
SLAVE
ADDRESS
N
N
O
OS
A
AT
C
CO
K
KP
SLAVE
X = Don’t Care
AN
C or O
KA
C
K
Dummy
DATA
Dummy
DATA
Figure 14. RPS & RPA Timing
www.onsemi.com
9