N34TS04 Datasheet, PDF (5/18 Pages) ON Semiconductor – Digital Output Temperature Sensor

SCL FROM
MASTER
N34TS04
1
8
9
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
START
Figure 4. Acknowledge Timing
ACKNOWLEDGE
SCL
70%
t_SU:STA
SDA IN
t_F
t_LOW
70%
30%
t_HD:STA
70%
30%
SDA OUT
t_HIGH
t_R
70%
30%
t_HD:DAT
70%
t_SU:DAT
30%
t_DH
70%
30%
Figure 5. Bus Timing
70%
30%
t_SU:STO
70%
70%
t_BUF
Table 7. COMMAND SET (Notes 9, 10)
Function Specific Preamble
Select Address
R/W_n
A0 Pin
Function
Read Temperature Registers
Abbr
RTR
b7
b6
b5
b4
b3
b2
b1
b0
0
0
1
1
LSA2 LSA1 LSA0
1
0 or 1
Write Temperature Registers
WTR
0
Read EE Memory
RSPD
1
0
1
0
LSA2 LSA1 LSA0
1
0 or 1
Write EE Memory
WSPD
0
Set Write Protection, block 0
SWP0
0
1
1
0
0
0
1
0
V_HV
Set Write Protection, block 1
SWP1
1
0
0
0
V_HV
Set Write Protection, block 2
SWP2
1
0
1
0
V_HV
Set Write Protection, block 3
SWP3
0
0
0
0
V_HV
Clear All Write Protection
CWP
0
1
1
0
V_HV
Read Protection Status, block 0 RPS0
0
0
1
1
0, 1 or V_HV
Read Protection Status, block 1 RPS1
1
0
0
1
0, 1 or V_HV
Read Protection Status, block 2 RPS2
1
0
1
1
0, 1 or V_HV
Read Protection Status, block 3 RPS3
0
0
0
1
0, 1 or V_HV
Set SPD Page Address to 0
(Select Lower Bank)
SPA0
1
1
0
0
0, 1 or V_HV
Set SPD Page Address to 1
(Select Upper Bank)
SPA1
1
1
1
0
0, 1 or V_HV
Read SPD Page Address
RPA
1
1
0
1
0, 1 or V_HV
Reserved
−
All Other Encodings
9. LSAx stands for Logic State of Address pin x.
10. If V_HV is not applied on the A0 pin during SWP/CWP commands, the N34TS04 will respond with NoACK after the 3rd byte and will not execute
the SWP/CWP instruction. During RPS/SPA/RPA commands the state of pin A0 must be stable for the duration of the sequence.
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