N34TS04 Datasheet, PDF (3/18 Pages) ON Semiconductor – Digital Output Temperature Sensor

N34TS04
Table 5. A.C. CHARACTERISTICS (V_CC = 1.7 V to 5.5 V, T_A = −40°C to +125°C)
Symbol
Parameter
Min
Max
Units
F_SCL (Note 5)
Clock Frequency
0.01
1
MHz
t_HIGH
High Period of SCL Clock
260
ns
t_LOW
Low Period of SCL Clock
500
ns
t_TIMEOUT (Note 6)
SMBus SCL Clock Low Timeout
25
35
ms
t_R (Note 7)
SDA and SCL Rise Time
120
ns
t_F (Note 7)
SDA and SCL Fall Time
120
ns
t_SU:DAT
Input Data Setup Time
50
ns
t_SU:STA
START Condition Setup Time
260
ns
t_HD:STA
START Condition Hold Time
260
ns
t_SU:STO
STOP Condition Setup Time
260
ns
t_BUF
Bus Free Time Between STOP and START
500
ns
t_HD:DAT
Input Data Hold Time
0
ns
t_DH (Note 7)
Output Data Hold Time
120
300
ns
T_i
Noise Pulse Filtered at SCL and SDA Inputs
50
ns
t_WR
Write Cycle Time
5
ms
t_PU (Note 8)
Power-Up Delay to Valid Temperature Recording
100
ms
5. Test conditions according to AC Test Conditions table. Bus loading must be such as to allow meeting the V_IL and V_OL as well as all other
timing requirements. The minimum clock frequency of 10 kHz is an SMBus recommendation; the minimum operating clock frequency is
limited only by the SMBus time−out. The device also meets the Fast and Standard I²C specifications, except that T_i and t_DH are shorter, as
required by the 1 MHz Fast Plus protocol.
6. For the N34TS04, the interface will reset itself and will release the SDA line if the SCL line stays low beyond the t_TIMEOUT limit. The time−out
count takes place when SCL is low in the time interval between START and STOP.
7. In a “Wired−OR” system (such as I²C or SMBus), SDA rise time is determined by bus loading. Since each bus pull−down device must be
able to sink the (external) bus pull−up current (in order to meet the V_IL and/or V_OL limits), it follows that SDA fall time is inherently faster than
SDA rise time. SDA rise time can exceed the standard recommended t_R limit, as long as it does not exceed t_LOW − t_DH − t_SU:DAT, where t_LOW
and t_DH are actual values (rather than spec limits). A shorter t_DH leaves more room for a longer SDA t_R, allowing for a more capacitive bus
or a larger bus pull−up resistor.
8. The first valid temperature recording can be expected after t_PU at nominal supply voltage.
Table 6. PIN CAPACITANCE (T_A = 25°C, V_CC = 3.6 V, f = 1 MHz)
Symbol
Parameter
Test Conditions/Comments
Min
Max
Unit
C_IN
SDA, EVENT Pin Capacitance
Input Capacitance (other pins)
V_IN = 0
V_IN = 0
8
pF
6
pF
10
300 ns Rise Time
120 ns Rise Time
1
SDA
0.1
10
100
LOAD CAPACITANCE (pF)
Figure 2. Pull−up Resistance vs. Load Capacitance
V_CC
R_L
C_L
V_SS
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