N34TS04 Datasheet, PDF (12/18 Pages) ON Semiconductor – Digital Output Temperature Sensor

N34TS04
Table 12. CONFIGURATION REGISTER
B15
B14
B13
RFU
RFU
RFU
B7
B6
B5
TCRIT_LOCK ALARM_LOCK CLEAR
B12
RFU
B4
EVENT_STS
B11
RFU
B3
EVENT_CTRL
B10
B9
HYST [1:0]
B2
B1
TCRIT_ONLY EVENT_POL
B8
SHDN
B0
EVENT_MODE
Bit
Description
B15:B11
Reserved for future use; can not be written; should be ignored; will read as 0
B10:B9 (Note 18)
00: Disable hysteresis
01: Set hysteresis at 1.5°C
10: Set hysteresis at 3°C
11: Set hysteresis at 6°C
B8 (Note 22)
0: Thermal Sensor is enabled; temperature readings are updated at sampling rate
1: Thermal Sensor is shut down; temperature reading is frozen to value recorded before SHDN
B7 (Note 21)
0: Critical trip register can be updated
1: Critical trip register cannot be modified; this bit can be cleared only at POR
B6 (Note 21)
0: Alarm trip registers can be updated
1: Alarm trip registers cannot be modified; this bit can be cleared only at POR
B5 (Note 20)
0: Always reads as 0 (self−clearing)
1: Writing a 1 to this position clears an event recording in interrupt mode only
B4 (Note 19)
0: EVENT output pin is not being asserted
1: EVENT output pin is being asserted
B3 (Note 18)
0: EVENT output disabled; polarity dependent: open−drain for B1 = 0; grounded for B1 = 1
1: EVENT output enabled
B2 (Note 24)
0: event condition triggered by alarm or critical temperature limit crossing
1: event condition triggered by critical temperature limit crossing only
B1 (Notes 18, 23)
0: EVENT output active low
1: EVENT output active high
B0 (Note 18)
0: Comparator mode
1: Interrupt mode
18. Can not be altered (set or cleared) as long as either one of the two lock bits, B6 or B7 is set.
19. This bit is a polarity independent ‘software’ copy of the EVENT pin, i.e. it is under the control of B3. This bit is read−only.
20. Writing a ‘1’ to this bit clears an event condition in Interrupt mode, but has no effect in comparator mode. When read, this bit always returns
0. Once the measured temperature exceeds the critical limit, setting this bit has no effect (see Figure 15).
21. Cleared at power−on reset (POR). Once set, this bit can only be cleared by a POR condition.
22. The TS powers up into active mode, i.e. this bit is cleared at power−on reset (POR). When the TS is shut down the ADC is disabled and the
temperature reading is frozen to the most recently recorded value. The TS can not be shut down (B8 can not be set) as long as either one
of the two lock bits, B6 or B7 is set. However, the bit can be cleared at any time.
23. The EVENT output is “open−drain” and requires an external pull−up resistor for either polarity. The “natural” polarity is “active low”, as it allows
“wired−or” operation on the EVENT bus.
24. Can not be set as long as lock bit B6 is set.
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