N25S830HA_14 Datasheet, PDF (8/12 Pages) ON Semiconductor – 256 kb Low Power Serial SRAMs

N25S830HA
SI
16−bit address
Page address (X)
Word address (Y)
SO
Data Words: sequential, at the end of the page the
address wraps back to the beginning of the page
Page X Page X Page X
Word Y Word Y+1 Word Y+2
Page X Page X
Word 31 Word 0
Figure 8. Page READ Sequence
Page X
Word 1
SI
16−bit address
Page address (X)
Word address (Y)
SO
Page X
Word Y
Data Words: sequential, at the end of the page the address wraps to the beginning
of the page and continues incrementing up to the starting word address. At that
time, the address increments to the next page and the burst continues.
...
...
Page X
Word Y+1
Page X Page X+1 Page X+1
Word 31 Word 0 Word 1
Figure 9. Burst READ Sequence
Page X+1 Page X+2 Page X+2
Word 31 Word 0 Word 1
WRITE Operations
The serial SRAM WRITE is selected by enabling CS low.
First, the 8−bit WRITE instruction is transmitted to the
device followed by the 16−bit address with the MSB being
a don’t care. After the WRITE instruction and addresses are
sent, the data to be stored in memory is shifted in on the SI
pin.
If operating in page mode, after the initial word of data is
shifted in, additional data words can be written as long as the
address requested is sequential on the same page. Simply
write the data on SI pin and continue to provide clock pulses.
The internal address pointer is automatically incremented to
the next higher address on the page after each word of data
is written in. This can be continued for the entire page length
of 32 words long. At the end of the page, the addresses
pointer will be wrapped to the 0 word address within the
page and the operation can be continuously looped over the
32 words of the same page. The new data will replace data
already stored in the memory locations.
If operating in burst mode, after the initial word of data is
shifted in, additional data words can be written to the next
sequential memory locations by continuing to provide clock
pulses. The internal address pointer is automatically
incremented to the next higher address after each word of
data is read out. This can be continued for the entire array
and when the highest address is reached (7FFFh), the
address counter wraps to the address 0000h. This allows the
burst write cycle to be continued indefinitely. Again, the new
data will replace data already stored in the memory
locations.
All WRITE operations are terminated by pulling CS high.
CS
SCK
0 1 2 3 4 5 6 7 8 9 10 11 21 22 23 24 25 26 27 28 29 30 31
Instruction
16−bit address
Data In
SI _{0 0 0 0 0 0 1 0 15 14 13 12} ... _{2 1 0 7 6 5 4 3 2 1 0}
SO
High−Z
Figure 10. Word WRITE Sequence
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