N25S830HA_14 Datasheet, PDF (4/12 Pages) ON Semiconductor – 256 kb Low Power Serial SRAMs

Table 6. TIMING TEST CONDITIONS
Item
Input Pulse Level
Input Rise and Fall Time
Input and Output Timing Reference Levels
Output Load
Operating Temperature
Table 7. TIMING
Item
Clock Frequency
Clock Rise Time
Clock Fall Time
Clock High Time
Clock Low Time
Clock Delay Time
CS Setup Time
CS Hold Time
CS Disable Time
SCK to CS
Data Setup Time
Data Hold Time
Output Valid From Clock Low
Output Hold Time
Output Disable Time
HOLD Setup Time
HOLD Hold Time
HOLD Low to Output High−Z
HOLD High to Output Valid
N25S830HA
Symbol
f_CLK
t_R
t_F
t_HI
t_LO
t_CLD
t_CSS
t_CSH
t_CSD
t_SCS
t_SU
t_HD
t_V
t_HO
t_DIS
t_HS
t_HH
t_HZ
t_HV
0.1 V_CC to 0.9 V_CC
5 ns
0.5 V_CC
CL = 100 pF
−40 to +85°C
Min
Max
20
2
2
25
25
25
25
50
25
5
10
10
25
0
20
10
10
10
50
Units
MHz
ms
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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