N25S830HA_14 Datasheet, PDF (10/12 Pages) ON Semiconductor – 256 kb Low Power Serial SRAMs

N25S830HA
WRITE Status Register Instruction (WRSR)
This instruction provides the ability to write the status
register and select among several operating modes. Several
of the register bits must be set to a low ‘0’ if any of the other
bits are written. The timing sequence to write to the status
register is shown below, followed by the organization of the
status register.
CS
SCK
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Instruction
Status Register Data In
SI
0000000176543210
SO
High−Z
Figure 14. WRITE Status Register Sequence
Bit 7 Bit 6
Bit 5
Bit 4 Bit 3
Bit 2
Bit 1
Bit 0
Mode
0 0 = Word Mode (Default)
1 0 = Page Mode
0 1 = Burst Mode
1 1 = Reserved
Reserved
Must = 0
Reserved
Must = 0
Figure 15. Status Register
Hold Function
0 = Hold (Default)
1 = No Hold
READ Status Register Instruction (RDSR)
This instruction provides the ability to read the Status register. The register may be read at any time by performing the
following timing sequence.
CS
SCK
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Instruction
SI
00000101
Status Register Data Out
SO
High−Z
76543210
Figure 16. READ Status Register Instruction (RDSR)
Power−Up State
The serial SRAM enters a know state at power−up time. The device is in low−power standby state with CS = 1. A low level
on CS is required to enter an active state.
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