AND8001 Datasheet, PDF (7/8 Pages) ON Semiconductor – ODD NUMBER DIVIDE BY COUNTERS WITH 50% OUTPUTS AND SYNCHRONOUS CLOCKS

Maps show:
Ja = 1 JB = AC*
Ka = 1
Kb = A
Jc = AB
Kc = A
AND8001/D
Figure 8 shows the implementation.
J
Q
H
A
J
Q
B
J
Q
C
J
Q
D
50% Out
K
Q
C
Clk
K
Q
C
K
Q
C
K
Q
C
Ja = 1
Ka = 1
Jb = AC
Kb = A
Jc = AB
Kc = A
Jd = ACD
Kd = ACD
CLK
AQ
BQ
CQ
OUT, DQ
Figure 8. Synchronous Divide By 12
ABCD
00000
11000
20100
31100
40010
5 1 0 1 0*
60001
71001
80101
91101
10 0 0 1 1
11 1 0 1 1*
The truth table shows that the FF ”D”
must change state at 5 and 13
Examination of the truth table shows that the FF ”D” must
decode a 5 and a 13 in order to make the desire 50% function.
The inputs to the ”D” FF are J = ACD* and K = ACD and
requires 3 input AND gates. For larger counters the inputs
on the AND gates will need to increase to reach the desired
configuration; However for the single digit integers such as
3, 5, 7, & 9 to realize 6, 10, 14, & 18 a fan in of three is max.
The methods are expandable. A little observation,
thinking, and logic typing will allow the designer to
minimize the component count and skew on this type of
counter.
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