AND8001 Datasheet, PDF (5/8 Pages) ON Semiconductor – ODD NUMBER DIVIDE BY COUNTERS WITH 50% OUTPUTS AND SYNCHRONOUS CLOCKS

AND8001/D
Take the before mentioned Divide By 3 add a J K and a
divide by 6, 50% duty cycle, synchronous counter is realized
as shown in Figure 5.
DQ
A
Q
C
Clk
Clk
AQ
BQ
OUT, CQ
DQ
B
Q
C
Divide By 6 50% Out
Figure 5.
J
Q
C
K
Q
C
50% Out
Of course, there are better ways to realize a Divide By 6
but it does demonstrate how the method works. Note this
configuration does not require a 50% input clock duty cycle
and it is synchronous. This type of configuration could be
useful in a clock generating PLL chip where a Divide By 3
and Divide By 6 are needed to synchronize two signals as
shown in figure 6.
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5