AND8001 Datasheet, PDF (1/8 Pages) ON Semiconductor – ODD NUMBER DIVIDE BY COUNTERS WITH 50% OUTPUTS AND SYNCHRONOUS CLOCKS

AND8001/D
OCanoddudnSNtyeunrmscbhWeroirtnhDoi5uv0sid%CelOoBcuyktpsuts
Prepared by: Cleon Petty and Paul Shockman
Product Applications
ON Semiconductor
The application inquiries handled by the Product
Applications gives opportunities to solve customer needs
with new ideas and learn of ways the customer has used our
devices in new applications. A couple of these calls lead to
techniques of designing odd number counters with
synchronous clocks and 50% outputs.
The first technique requires a differential clock, that has
a 50% duty cycle, a extra Flip Flop, and a gate to allow Odd
integers, such as 3, 5, 7, 9, to have 50% duty cycle outputs
and a synchronous clock. The frequency of operations is
limited by Tpd of the driving FF, Setup, and Hold of the extra
FF, and the times cannot exceed one half on the incoming
clock cycle time.
The design begins with producing a odd number counter
(Divide By 3 for this discussion) by any means one wishes
http://onsemi.com
APPLICATION NOTE
and add a flip flop, and a couple of gates to produce the
desired function. Karnaugh maps usually produce counters
that are lockup immune.
Example:
Specify,
Divide By 3,
50% duty cycle on the output
Synchronous clocking
50% duty cycle clock in
Using D type Flop flips and karnaugh maps we find;
Ad = A*B* and Bd = A
(Note: * indicates BAR function)
Figure 1 shows schematic and timing of such a design.
DQ
A
Q
C
DQ
B
Q
C
Divide By 3
Figure 1.
© Semiconductor Components Industries, LLC, 1999
1
October, 1999 – Rev. 0
Publication Order Number:
AND8001/D